ROM load balancing for bit lines

Details ROM load balancing for bit lines ROM load balancing for bit lines

2007-05-15

2007-05-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read only systems

C365S100000

Reexamination Certificate

active

11232767

ABSTRACT:
An apparatus and method to improve a cycle time of a Read Only Memory (ROM). Loading of each bit line is controlled such that no bit line has less than a specified loading fraction of a loading of a maximally loaded bit line. No additional space or additional circuitry is required. Four NFET pair arrangements are personalizable by via placement by a designer or design automation program. One of the NFET pair arrangements is usable to pad load on a bit line without altering a logical personalization of the bit line. Proper selection from the four NFET pair arrangements ensure that no bit line has less than the specified loading fraction of the loading of the maximally loaded bit line, as well as providing proper logical personality of the bit line.

REFERENCES:
patent: 5777922 (1998-07-01), Choi et al.
patent: 6157569 (2000-12-01), Nomura et al.
patent: 6791860 (2004-09-01), Chen
patent: 6795350 (2004-09-01), Chen et al.
R.R. Williams and P. Wu, IBM Technical Disclosure Bulletin, “Read-Only Storage Data Inversion for Speed Enhancement”, vol. 22, No. 8B, Jan. 1980, pp. 3793-3794.

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