ROM data verification circuit

Details ROM data verification circuit ROM data verification circuit

1998-12-30

2001-07-24

Shah, Kamini (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C365S189120, C714S718000

Reexamination Certificate

active

06266626

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a read only memory (ROM) data verification circuit for checking whether or not data have correctly been written into a ROM device (or a ROM) or into a plurality of ROM devices (or a plurality of ROMs).
2. Description of the Prior Art
FIG. 9
is a block diagram showing a configuration of a conventional ROM data verification circuit. In
FIG. 9
, the reference number
91
designates a Read Only Memory (ROM) for storing programs and data items, the reference number
94
denotes output ports through which addresses from a Central Processing Unit (CPU) and data items from the ROM
91
are output externally, and the reference number
93
indicates the CPU for controlling the operation of the ROM
91
and the output ports
4
.
Next, a description will be given of the operation of the conventional ROM data verification circuit.
FIG. 10
is a flow chart showing the operation of the conventional ROM data verification circuit shown in FIG.
9
.
In order to check whether data such as programs, control data, and other types of data have correctly been written into the ROM
91
, the conventional ROM data verification circuit performs the following test.
First, the CPU
93
in the conventional ROM data verification circuit executes an instruction “MOV” as one of instructions described in a test program, so that data written and stored in the ROM
91
are read out per byte. Then, the data that have been read out are output to external devices (not shown) through the output ports
94
(Step ST
102
). Next, the data read out are compared with expected data that have been prepared in advance (Step ST
103
). Based on the comparison result obtained by the step ST
103
, it is possible to verify whether the data have correctly been written into the ROM
91
. The completion of the comparison operation for all of data items stored in the ROM
91
(Step ST
104
) leads the completion of the test operation.
Since the conventional ROM data verification circuit has the configuration described above, the data size that are read out from the ROM
91
at once is small, so that it takes a long time period to perform the test operation for the data stored in the ROM
91
. Recently, the memory size (or the volume) of ROM devices is increasing and the amount of data to be stored in the ROM devices is also increasing. This causes to increase the time period of the test operation to be required for checking whether or not data have correctly been stored into ROM devices. In addition, the size of test programs and test vectors to be used for testing data stored in the ROM devices are increased. This also causes to increase the time period of the test operation.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a ROM data verification circuit for precisely checking whether data have correctly been written into a ROM or a plurality of ROMs at a high speed rate. In addition, another object of the present invention is to provide a ROM data verification circuit for reducing the number of test vectors and a time period of test operation by using a test program in a smaller size.
In accordance with a preferred embodiment of the present invention, a ROM data verification circuit to be used for checking data stored in a ROM, comprises control means for directly reading out data stored in the ROM when a CPU abandons to use an address bus and a data bus, for dividing the data that have been read out from the ROM into a plurality of divided data, and for generating a plurality of addresses according to which the plurality of divided data are transferred, and a plurality of output ports indicated by the addresses generated by and transferred from the control means to which the plurality of divided data are transferred by the control means according to the addresses.
The ROM data verification circuit as another preferred embodiment according to the present invention, further comprises a first register to which control data indicating to abandon the use of the address bus and the the data bus by the CPU are set, wherein the control means is a Direct Memory Access Controller, and the DMAC commences to read the data stored in the ROM when the control data are stored into the first register.
The ROM data verification circuit as another preferred embodiment according to the present invention, further comprises an address pointer for generating addresses corresponding to the plurality of output ports, wherein the control means is a Direct Memory Access Controller, and the divided data outputted from the DAMC are transferred to each of the plurality of output ports designated by the corresponding address generated by the address pointer.
In the ROM data verification circuit as another preferred embodiment according to the present invention, The ROM data verification circuit as another preferred embodiment according to the present invention, the control means comprises first control means, second control means, a second register placed between the first control means and the second control means, and a Direct Memory Access Controller (DMAC) synchronous circuit, and wherein under control of the DMAC synchronous circuit, operation of both the first control means and the second control means is synchronized, the first control means reads out the data stored in the ROM and stores the data into the second register, and the second control means reads and then divides the data stored in the second register into a plurality of divided data and generates addresses to indicate the plurality of output ports and outputs the plurality of divided data to the plurality of output ports indicated by the addresses generated by the second control means.
In the ROM data verification circuit as another preferred embodiment according to the present invention, the control means is a dedicated address counter, and the ROM comprises a plurality of ROM devices, and the ROM data verification circuit further comprises dedicated address buses and dedicated data buses, placed corresponding to the output ports, through which the data read from the plurality of ROM devices are transferred to the plurality of output ports, and wherein the dedicated address counter generates the addresses to indicate the data stored in the plurality of ROM devices and outputs the addresses to the ROM devices through the dedicated address buses, and reads the data from the plurality of ROM devices and then transfers the data that have been read out into the plurality of corresponding output ports.
In the ROM data verification circuit as another preferred embodiment according to the present invention, the ROM comprises a plurality of ROM devices, the control means is a Central Processing Unit including a program counter, and the ROM data verification circuit further comprises dedicated address buses and dedicated data buses, placed corresponding to the plurality of output ports, through which the data read from the plurality of ROM devices are transferred to the plurality of output ports, and wherein the program counter in the CPU generates addressed to indicate the data stored in the plurality of ROM devices, outputs the addresses to the plurality of ROM devices through the dedicated address buses and reads the data and outputs the data that have been read out to the plurality of output ports through the dedicated data buses.
In the ROM data verification circuit as another preferred embodiment according to the present invention, the dedicated address counter simultaneously generates a plurality of addresses to indicate data stored in the plurality of ROM devices, and simultaneously reads the data from the plurality of ROM devices by using the plurality of addresses generated, and outputs the data to the plurality of corresponding output ports through the dedicated data buses.
In the ROM data verification circuit as another preferred embodiment according to the present invention, the control mean

Affiliated with

Also associated with

Rating

ROM data verification circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ROM data verification circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ROM data verification circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2437837