Boots – shoes – and leggings
Patent
1980-03-17
1982-01-26
Malzahn, David H.
Boots, shoes, and leggings
364757, G06F 7544, G06F 7552
Patent
active
043131743
ABSTRACT:
A fully-parallel digital arithmetic device for obtaining the square, C.sup.2, of a value, C, via parts of the value C and involving a reduction in memory requirements. Three square function ROM's are employed, one responsive to the most significant-bits half of a parallel input, the second ROM responsive to the least-significant bits half of the parallel input, and the third one responsive to the sum of said most significant bits and least-significant bits. The outputs of the square function ROM's are then combined and scaled to effect a square by parts of the applied input value, C. A pair of such arithmetic devices may be advantageously combined to economically effect the product AB of two values, A and B, in the manner of a quarter square multiplier.
REFERENCES:
patent: 3610906 (1971-10-01), Stampler
patent: 3749898 (1973-07-01), Logan
patent: 3917935 (1975-11-01), Lazecki
Jayashree et al. "On Binary Multiplication Using the Quarter Square, Algorithm", IEEE Trans-on Computers, Sep. 1976, pp. 957-960.
Caplener et al "High-Speed Parallel Digital Multiplier", IBM Technical Disclosure Bulletin vol. 12, No. 5, Oct. 1969, p. 685.
Singh "Binary Multiplier Circuit Using Read-Only Memory", IBM Tech. Disclosure Bulletin vol. 14, No. 10, Mar. 1972, pp. 2981-2982.
Hamann H. Fredrick
Malzahn David H.
Pitts Rolf M.
Rockwell International Corporation
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