ROM array with shared bit-lines

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S185030

Reexamination Certificate

active

08059442

ABSTRACT:
Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.

REFERENCES:
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patent: 7031179 (2006-04-01), Yon et al.
patent: 2003/0141532 (2003-07-01), Kato
patent: 2005/0174841 (2005-08-01), Ho
patent: 2006/0239071 (2006-10-01), Ohta
patent: 2009/0303769 (2009-12-01), Alami et al.
“U.S. Appl. No. 12/136,400, Non-Final Office Action mailed Jan. 11, 2010”, 10 pgs.
“U.S. Appl. No. 12/136,400, Notice of Allowance mailed Apr. 30, 2010”, 7 pgs.
“U.S. Appl. No. 12/136,400, Response filed Apr. 6, 2010 to Non Final Office Action mailed Jan. 11, 2010”, 6 pgs.
“High Density Non-Volatile Memory Array”, U.S. Appl. No. 11/749,428, filed May 16, 2007, 45 pages.

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