Robust delay fault built-in self-testing method and apparatus

Details Robust delay fault built-in self-testing method and apparatus Robust delay fault built-in self-testing method and apparatus

1993-07-23

1995-06-06

Cosimano, Edward R.

Excavating

364488, 364578, 371 221, 371 251, 371 27, G06F 1750

Patent

active

054228913

ABSTRACT:
This invention relates to a method and apparatus for robust delay fault testing of integrated circuits (IC) with built-in self-testing. For the method, hazardous nodes of the IC are determined. Thereafter, the topology of the IC can be modified to include a cut-point at hazardous nodes of the circuit. Input of the IC to the cut-point is diverted to an observation point. An out-put multi-input signature register (MISR) at the observation point generates a first signature. An output MISR provides a second signature for outputs to the IC. During testing, a hazard-free input pattern is applied to the IC and the generated first and second signatures are compared to known correct signatures.

REFERENCES:
patent: 4495621 (1985-01-01), Nakagomi et al.
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4656592 (1987-04-01), Spaanenburg et al.
patent: 4672307 (1987-06-01), Breuer et al.
patent: 4687988 (1987-08-01), Eichelberger et al.
patent: 4688223 (1987-08-01), Motika et al.
patent: 4745355 (1988-05-01), Eichelberger et al.
patent: 4787062 (1988-11-01), Nei et al.
patent: 4801870 (1989-01-01), Eichelberger et al.
patent: 4893072 (1990-01-01), Matsumoto
patent: 4897837 (1990-01-01), Ishihara et al.
patent: 4939677 (1990-07-01), Otuji et al.
patent: 4965474 (1990-10-01), Childers et al.
patent: 5023875 (1991-06-01), Lee et al.
patent: 5051996 (1990-09-01), Bergeson et al.
patent: 5056094 (1991-10-01), Whetsel
patent: 5065090 (1991-11-01), Gheewala
patent: 5091872 (1992-02-01), Agrawal
patent: 5095483 (1992-03-01), Dubler et al.
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5184067 (1993-02-01), Nozuyama
Design for Testability for Path Delay Faults in Sequential Circuits by Tapan J. Chakraborty, Vishwani D. Agrawal and Michael L. Bushnell (no date).
Delay Fault Models and Test Generation for Random Logic Sequential Circuits, Tapan J. Chakroborty, Vishwani D. Agrawal and Michael Bushnell, 29th ACM/IEEE Design Automation Conference.
On Delay Fault Testing in Logic Circuits, Chin Jen Lin and Sudhakar M. Reddy, 1987 IEEE Transactions on Computer Aided Design, pp. 694-703.
Model for Delay Faults Based Upon Paths, Gordon L. Smith, 1985 International Test Conference, Paper 9.6, 342-349.
Efficient Test Converage Determination for Delay Faults, J. L. Carter, V. S. Iyengar and B. K. Rosen, IBM Thomas J. Watson Research Center.
A Delay Test Generator for Logic LSI, Terumini Hayashi, Kazumi Hatayama Katsuya Sato and Takashi Natabe, 1984 IEEE pp. 146-149.
Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults, Michael H. Schulz, Karl Fuchs and Frank Fink, 19th Symposium on Fault-Tolerant Computing 1989 pp. 1-8.

Affiliated with

Also associated with

Rating

Robust delay fault built-in self-testing method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Robust delay fault built-in self-testing method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Robust delay fault built-in self-testing method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-992856