Robust clock circuit architecture

Details Robust clock circuit architecture Robust clock circuit architecture

2002-09-06

2004-01-06

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S002000, C331S016000, C331S025000, C327S292000

Reexamination Certificate

active

06674332

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly but not exclusively to clock circuits.
2. Description of the Background Art
Various types of clock circuits are employed to provide timing information to other circuits. Examples of clock circuits include clock buffers, synthesizers, synchronizers, jitter attenuators, clock generators, clock recovery circuits, and the like. In some applications, one or more clock signals are generated by a clock circuit that is synchronized with an input reference signal. To provide continuous clock signals even when the reference signal is disrupted, some clock circuits include external back-up oscillators that may be used as a replacement for the reference signal. However, the change over from the reference signal to the back-up oscillator may take some time, and may thus result in a momentary glitch or clock signal loss. Also, the use of back-up oscillators may require additional circuitry, such as a multiplexer and a control circuit for switching-in the oscillator. From the foregoing, it is desirable to have a robust clock circuit that may continue to present clock signals even when its reference signal is disrupted. Advantageously, such a clock circuit should also be capable of presenting a clock signal that has a frequency different from that of the reference signal.
SUMMARY
In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.


REFERENCES:
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patent: 4980899 (1990-12-01), Troost et al.
patent: 5796392 (1998-08-01), Eglit
Network Synchronization Clock Family, MK2049 MK2058 MK2059. Timing Solutions For Every Application, pp. 1-8, Integrated Circuit Systems, Inc. 2001.
VCXO-Based Frame Clock Frequency Translator, MK2059-01, a based clock generator, pp. 1-10; Sep. 19, 2001 Revision, Integrated Circuit Systems, Inc.
3.3 V Communications Clock PLL, MK2049-36, a based clock synthesizer, pp. 1-9; Sep. 18, 2001 Revision, Integrated Circuit Systems, Inc.
Communications Clock Jitter Attenuator, MK 2058-01, a based clock jitter attenuator, pp. 1-10: Jul. 10, 2001 Revision, Integrated Circuit Systems, Inc.
Updated Values for External Loop Filter Components and other Useful information, MK2049-34/35/36 Errata, pp. 1-4; Jul. 12, 2001 Revision, Integrated Circuit Systems, Inc.
VCXO-Based Universal Clock Translator, MK2069-04, a based clock generator, pp. 1-19; Nov. 19, 2001 Revision, Integrated Circuit Systems, Inc.
SCG2000 Series Synchronous Clock Generators, pp. 1-20, Rev. AO4, Jan. 29, 2002, The Connor-Winfield Corporation.

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