Robust and high-speed memory access with adaptive interface...

Details Robust and high-speed memory access with adaptive interface... Robust and high-speed memory access with adaptive interface...

2006-06-13

2006-06-13

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S238500

Reexamination Certificate

active

07061804

ABSTRACT:
Techniques for quickly and reliably accessing a memory device (e.g., a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access. Error correction coding (ECC), which is often employed for NAND Flash memory, is then used to ensure reliable access of the NAND Flash. For a read operation, one page of data is read at a time from the NAND Flash memory, and the ECC determines whether the page read from the NAND Flash memory contains any errors. If errors are encountered, then a slower memory access rate is selected, and the page with error is read again from the NAND Flash memory at the new rate. The techniques may be used to write data to the NAND Flash memory.

REFERENCES:
patent: 5210870 (1993-05-01), Baum et al.
patent: 6657892 (2003-12-01), Sakui et al.
patent: 2003/0126392 (2003-07-01), Miura et al.

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