Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
1998-09-11
2002-01-01
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S213000, C712S209000
Reexamination Certificate
active
06336178
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to processors. More specifically, this invention relates to processors that convert an x86 instructions into RISC-type operations for execution on a RISC-type core.
2. Description of the Related Art
Advanced microprocessors, such as P6-class x86 processors, are defined by a common set of features. These features include a superscalar architecture and performance, decoding of multiple x86 instructions per cycle and conversion of the multiple x86 instructions into RISC-like operations. The RISC-like operations are executed out-of-order in a RISC-type core that is decoupled from decoding. These advanced microprocessors support large instruction windows for reordering instructions and for reordering memory references.
The conversion or translation of CISC-like instructions into RISC-like instructions typically involves a mapping of many like-type instructions, for example many variations of an ADD instruction, into one or more generic instructions. Furthermore, a very large number of addressing modes of a particular instruction are converted into a register-to-register operation in combination with load and store operations accessing memory. Performance of a microprocessor that converts CISC-type instructions into RISC-type instructions for execution depends greatly on the number of RISC-type operations produced from a single CISC-type instruction.
Performance of an advanced superscalar microprocessor is also highly dependent upon decoding performance including decoding speed, the number of x86 instructions decoded in a single cycle, and branch prediction performance and handling. Instruction decoders in advanced superscalar microprocessors often include one or more decoding pathways in which x86 instructions are decoded by hardware logic translation and a separate decoding pathway which uses a ROM memory for fetching a RISC operation sequence that corresponds to an x86 instruction. Generally, x86 instructions that are translated by hardware logic are simple x86 instructions. The lookup ROM is used to decode more complex x86 instructions.
One problem with the usage of lookup ROM for decoding x86 instructions is that the process of accessing a microprogram control store is inherently slower and less efficient than hardwired translation of instructions. A further problem arising with decoding of x86 instructions via lookup ROM is the very large number of different CISC-type instructions that are standard for an x86 processor. Since a substantial number of instructions are implemented, a large ROM circuit on the processor chip is necessary for converting the instructions to RISC-like operations. The large number of implemented instructions corresponds to an increased circuit complexity for deriving pointers to the ROM and applying the derived pointers to the ROM. This increased circuit complexity directly relates to an increased overhead that reduces instruction decoding throughput. A large lookup ROM increases the size of the processor integrated circuit and thereby reduces manufacturing yields of the circuits and increases production costs.
What is needed is an internal instruction format that facilitates translation of a very large number of CISC-type instructions into a small number of RISC-type operations. What is also needed is an internal instruction format that facilitates conversion of CISC-type instructions into a minimum number of RISC-type operations. What is further needed is an internal instruction format that permits more common CISC-type instructions to be converted using hardwired logic, as compared to conversion via lookup ROM.
SUMMARY OF THE INVENTION
In accordance with the present invention, an internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality of operation (Op) formats. One format includes an instruction-type bit field, two source-operand bit fields and one destination-operand bit field for designating a register-to-register operation. Another format is a load-store format that includes an instruction-type bit field, an identifier of a source or destination register for the respective load or store operation, and bit fields for specifying the segment, base and index parameters of an address, an index scaling factor and a displacement.
In accordance with a first embodiment of the present invention, a RISC-like internal instruction set executes on a RISC-like core of a superscalar processor. The RISC-like internal instruction set is translated from instructions of a CISC-like external instruction set. The instruction set includes a plurality of instruction codes arranged in a fixed bit-length structure. The structure being divided into a plurality of defined-usage bit fields. The instruction codes have a plurality of operation (Op) formats of the plurality of defined-usage bit fields. One Op format is a first register Op format having a format bit-field designating the instruction code as a first register Op format code, a type bit-field designating a register instruction type, a first source operand bit-field identifying a first source operand, a second source operand bit-field identifying a second source operand, a destination bit-field designating a destination operand, and an operand size bit-field designating an operand byte-size. A second Op format is a load-store Op format having a format bit-field designating the instruction code as a load-store Op format code, a type bit-field designating a load-store instruction type, a data bit-field identifying a destination-source of a load-store operation, an index scale factor bit-field for designating an index scale factor, a segment bit-field designating a segment register, a base bit-field designating a load-store base address, a displacement bit-field designating a load-store address displacement, and an index bit-field designating a load-store address index. Various bit-fields of the instruction code are substituted into the Op format with the substituted bit-field determined as a function of processor context.
Many advantages are gained by the described instruction set and instruction set format. One substantial advantage is that the described instruction set is highly regular with a fixed length and format of RISC operations. By comparison, conventional x86 instructions are highly irregular having greatly different instruction lengths and formats. A regular structure greatly reduces circuit complexity and size and substantially increases efficiency. A further advantage is that extensions are included for efficient mapping of operations by the decoder. The extensions support direct decoding and emulation or mapping of x86 instructions. Another advantage is that the described instruction set is implemented in a reduced ROM memory size due to reuse of operation structures for multiple variations that are common among x86 instructions. Usage of substitution achieves encoding of CISC functionality while substantially reducing the size of lookup code ROM, advantageously reducing the size and cost of a processor integrated circuit.
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Advanced Micro Devices , Inc.
Donaghue Larry D.
Skjerven Morrill & MacPherson LLP
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