RISC processor with a debug interface unit

Details RISC processor with a debug interface unit RISC processor with a debug interface unit

2000-10-30

2004-07-20

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S215000, C712S212000, C712S213000, C712S225000, C710S305000

Reexamination Certificate

active

06766438

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to processors and more specifically to a RISC processor having a debug interface unit.
2. Description of the Related Art
Multi-layer switching procedures and complex data protocols are carried out by processors or by Reduced Instruction Set Computers, (RISC Processors), particularly in switching systems. Typically, the RISC processor is dimensioned for the most efficient energy and space requirements and is optimized according to its applied purpose.
To promptly locate possible errors in the complex processing procedures, it is desirable to externally replicate the data processing procedures sequencing within the RISC processor. Yet, this requires an inquiry into a multitude of interrogation possibilities for registered contents of the RISC processor. Specifically, since the register contents at various locations of the pipeline of the RISC processor must be accessed during an error search, the access possibilities to the data that are intermediately stored in the registers in the pipeline of the RISC processor are difficult to configure. This likelihood of access to the register data stored in the pipeline of the RISC processor is further complicated when the RISC processor together with a program memory is integrated in an ASIC module.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a RISC processor with a debug interface unit. This debug interface unit is integrated within the data transfer unit of the RISC processor. Various type of data, including command data and their pertinent source address are intermediately stored within the various registers of the debug interface unit. These Data are then transmitted from the debug interface unit register content for evaluation by an outside operator.
One aspect of the present invention is that the register contents can be co-read in real time. This is an improvement over the prior systems. Also, the present invention demonstrates the additional advantage in that the area of a RISC processor need only be enlarged by the area of a pin when the input and output interface I of the RISC processor is co-utilized. Moreover, all required information for performing an efficient error search are displayed with the command data, address data and the pertinent destination and source data that may be monitored by an outside operator.


REFERENCES:
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patent: 5513363 (1996-04-01), Kumar et al.
patent: 5526482 (1996-06-01), Stallmo et al.
patent: 5564028 (1996-10-01), Swoboda et al.
patent: 0 764 903 (1997-03-01), None
Circello et al., “A Mechanism to Output Internal State Information During Idle Bus Cycles”, Motorola Technical Developments, Jun. 1994, vol. 22, pp. 24-26.

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