RISC processor supporting one or more uninterruptible...

Details RISC processor supporting one or more uninterruptible... RISC processor supporting one or more uninterruptible...

2005-09-13

2005-09-13

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S244000, C710S260000

Reexamination Certificate

active

06944746

ABSTRACT:
A system and method for processing instructions in a computer system comprising a processor and a co-processor communicatively coupled to the processor. Instructions are processed in the processor in an instruction pipeline. In the instruction pipeline, instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage. If a co-processor instruction is received by the processor, the co-processor instruction is held in the core processor until the co-processor instruction reaches the memory access stage, at which time the co-processor instruction is transmitted to the co-processor.

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