Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1995-06-16
1996-10-22
Lane, Jack A.
Static information storage and retrieval
Addressing
Plural blocks or banks
36518902, 36518905, 395405, 395403, G11C 800
Patent
active
055684424
ABSTRACT:
A RISC processor utilizes a segmented cache to reduce word line loading to reduce power consumption and increase speed. Address bit are predecoded to activate a selected segment. Groups of instructions are accessed from the cache in parallel and stored in register. The stored instructions are fetched from the register during sequential instruction execution to reduce the number of cache accesses.
REFERENCES:
patent: 4695981 (1987-09-01), Sikich et al.
patent: 4783767 (1988-11-01), Hamada
patent: 4817057 (1989-03-01), Kondo et al.
patent: 4918662 (1990-04-01), Kondo
patent: 4926384 (1990-05-01), Roy
patent: 4931994 (1990-06-01), Matsui et al.
patent: 5150330 (1992-09-01), Hag
patent: 5170375 (1992-12-01), Mattausch et al.
patent: 5263002 (1993-11-01), Suzuki et al.
patent: 5285323 (1994-02-01), Hetherington et al.
patent: 5293332 (1994-03-01), Shirai
patent: 5293343 (1994-03-01), Raab et al.
patent: 5305278 (1994-04-01), Inoue
patent: 5329492 (1994-07-01), Mochizuki
patent: 5367655 (1994-11-01), Grossman et al.
patent: 5388072 (1995-02-01), Matick et al.
Kaldani Givargis G.
Kowalczyk Andre
Lane Jack A.
Silicon Graphics Inc.
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