Risc processing unit which selectively isolates register windows

Details Risc processing unit which selectively isolates register windows Risc processing unit which selectively isolates register windows

1991-10-25

1992-10-27

Lee, Thomas C.

Boots, shoes, and leggings

395800, 395375, 364DIG1, 364231, 3642328, 364247, 364258, G06F 934

Patent

active

051596806

ABSTRACT:
An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.

REFERENCES:
patent: 4777587 (1988-11-01), Case et al.
patent: 4777588 (1988-11-01), Case et al.
patent: 4945510 (1990-07-01), Maeda et al.
Tamie et al. "Strategies for Managing the Register File in RISC" Nov. 1983.
Pendelton et al. "A 32-bit Microprocessor for Small talk" Oct. 1986.
A 32-Bit "NMOS Microprocessor with a large register file" Oct. 1986, Serburne et al.
Mokhoff, "Scalable RISC-based architecture yields 10-MIPS workstations" Jul. 9, 1986.
"Reduced Instruction Set Computer Architectures for VLSI", by Manolis G. H. Katevenis, pp. 42.gtoreq.64, MIT Press, 1985 (215 pages).

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