RISC microprocessor architecture implementing multiple typed reg

Details RISC microprocessor architecture implementing multiple typed reg RISC microprocessor architecture implementing multiple typed reg

1995-06-05

1996-09-24

Harrell, Robert B.

Boots, shoes, and leggings

395375, 36423223, 3642451, 364247, 364DIG1, 364258, 3642591, 364238, G06F 934

Patent

active

055600352

ABSTRACT:
A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

REFERENCES:
patent: 4212076 (1980-07-01), Conners
patent: 5125092 (1992-06-01), Prener
patent: 5201056 (1993-04-01), Daniel et al.
patent: 5241636 (1993-08-01), Kohn
patent: 5487156 (1996-01-01), Popescu et al.
Ruby B. Lee, "Precision Architecture," IEEE Computer, pp. 78-91, Jan. 1989.
Daryl Odnert et al., "Architecture and Computer Enhancements for PA-RISC Workstations," Proc. from IEEE Compcon, San Francisco, CA, pp. 214-218, Feb. 1991.
Maejima et al., "A 16-bit Microprocessor with Multi-Register Bank Architecture", Proc. Fall Joint Computer Conference, Nov. 2-6, 1986, pp. 1014-1019.
Groves et al., "An IBM Second Generation RISC Processor Architecture", 35th IEEE Computer Society International Conference, Feb. 26, 1990, pp. 166-172.
Miller et al., "Exploiting Large Register Sets", Microprocessors and Microsystems, vol. 14, No. 6, Jul. 1990, pp. 333-340.
Adams et al., "Utilising Low Level Parallelism in General Purpose Code: The HARP Project", Microprocessing and Microprogramming, vol. 29, No. 3, Oct. 1990, pp. 137-149.
Molnar et al. "Floating-Point Processor" 1989 IEEE.
Stevens et al; "HARP: A Parallel Pipelined RISC Processor"; Nov. 1989.
Birman et al; "Design of a High-Speed Arithmetic Datapath"; 1988.
Paterson et al. "A VLSI RISC" Computer Sep. 1982.

Affiliated with

Also associated with

Rating

RISC microprocessor architecture implementing multiple typed reg does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with RISC microprocessor architecture implementing multiple typed reg, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and RISC microprocessor architecture implementing multiple typed reg will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1948349