Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
2000-01-10
2001-06-19
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S205000
Reexamination Certificate
active
06249856
ABSTRACT:
Applications of particular interest to the present application, include:
1. High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution, application Ser. No. 07/817,810, filed Jan. 8, 1992, now U.S. Pat. No. 5,539,911, by Le Trong Nguyen et al.;
2. High-Performance Superscalar-Based Computer System with Out-of-Order Instruction Execution and Concurrent Results Distribution, application Ser. No. 08/397,016, filed Mar. 1, 1995, now U.S. Pat. No. 5,560,032, by Quang Trang et al.;
3. RISC Microprocessor Architecture with Isolated Architectural Dependencies, application Ser. No. 08/292,177, filed Aug. 18, 1994, now abandoned, which is a FWC of application Ser. No. 07/817,807, filed Jan. 8, 1992, now abandoned, which is a continuation of application Ser. No. 07/726,744, filed Jul. 8, 1991, by Yoshiyuki Miyayama, now abandoned;
4. RISC Microprocessor Architecture Implementing Fast Trap and Exception State, application Ser. No. 08/345,333, filed Nov. 21, 1994, now U.S. Pat. No. 5,481,685, by Quang Trang;
5. Page Printer Controller Including a Single Chip Superscalar Microprocessor with Graphics Functional Units, application Ser. No. 08/267,646, filed Jun. 28, 1994, now U.S. Pat. No. 5,394,515, by Derek Lentz et al.; and
6. Microprocessor Architecture Capable with a Switch Network for Data Transfer Between Cache, Memory Port, and IOU, application Ser. No. 07/726,893, filed Jul. 8, 1991, now U.S. Pat. No. 5,440,752, by Derek Lentz et al.
The above-identified Applications are hereby incorporated herein by reference, their collective teachings being part of the present disclosure.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microprocessors, and more specifically to a RISC microprocessor having plural, symmetrical sets of registers.
2. Description of the Background
In addition to the usual complement of main memory storage and secondary permanent storage, a microprocessor-based computer system typically also includes one or more general purpose data registers, one or more address registers, and one or more status flags. Previous systems have included integer registers for holding integer data and floating point registers for holding floating point data. Typically, the status flags are used for indicating certain conditions resulting from the most recently executed operation. There generally are status flags for indicating whether, in the previous operation: a carry occurred, a negative number resulted, and/or a zero resulted.
These flags prove useful in determining the outcome of conditional branching within the flow of program control. For example, if it is desired to compare a first number to a second number and upon the conditions that the two are equal, to branch to a given subroutine, the microprocessor may compare the two numbers by subtracting one from the other, and setting or clearing the appropriate condition flags. The numerical value of the result of the subtraction need not be stored. A conditional branch instruction may then be executed, conditioned upon the status of the zero flag. While being simple to implement, this scheme lacks flexibility and power. Once the comparison has been performed, no further numerical or other operations may be performed before the conditional branch upon the appropriate flag; otherwise, the intervening instructions will overwrite the condition flag values resulting from the comparison, likely causing erroneous branching. The scheme is further complicated by the fact that it may be desirable to form greatly complex tests for branching, rather than the simple equality example given above.
For example, assume that the program should branch to the subroutine only upon the condition that a first number is greater than a second number, and a third number is less than a fourth number, and a fifth number is equal to a sixth number. It would be necessary for previous microprocessors to perform a lengthy series of comparisons heavily interspersed with conditional branches. A particularly undesirable feature of this serial scheme of comparing and branching is observed in any microprocessor having an instruction pipeline.
In a pipelined microprocessor, more than one instruction is being executed at any given time, with the plural instructions being in different stages of execution at any given moment. This provides for vastly improved throughput. A typical pipeline microprocessor may include pipeline stages for: (a) fetching an instruction, (b) decoding the instruction, (c) obtaining the instruction's operands, (d) executing the instruction, and (e) storing the results. The problem arises when a conditional branch instruction is fetched. It may be the case that the conditional branch's condition cannot yet be tested, as the operands may not yet be calculated, if they are to result from operations which are yet in the pipeline. This results in a “pipeline stall”, which dramatically slows down the processor.
Another shortcoming of previous microprocessor-based systems is that they have included only a single set of registers of any given data type. In previous architectures, when an increased number of registers has been desired within a given data type, the solution has been simply to increase the size of the single set of those type of registers. This may result in addressing problems, access conflict problems, and symmetry problems.
On a similar note, previous architectures have restricted each given register set to one respective numerical data type. Various prior systems have allowed general purpose registers to hold either numerical data or address “data”, but the present application will not use the term “data” to include addresses. What is intended may be best understood with reference to two prior systems. The Intel 8085 microprocessor includes a register pair “HL” which can be used to hold either two bytes of numerical data or one two-byte address. The present application's improvement is not directed to that issue. More on point, the Intel 80486 microprocessor includes a set of general purpose integer data registers and a set of floating point registers, with each set being limited to its respective data type, at least for purposes of direct register usage by arithmetic and logic units.
This proves wasteful of the microprocessor's resources, such as the available silicon area, when the microprocessor is performing operations which do not involve both data types. For example, user applications frequently involve exclusively integer operations, and perform no floating point operations whatsoever. When such a user application is run on a previous microprocessor which includes floating point registers (such as the 80486), those floating point registers remain idle during the entire execution.
Another problem with previous microprocessor register set architecture is observed in context switching or state switching between a user application and a higher access privilege level entity such as the operating system kernel. When control within the microprocessor switches context, mode, or state, the operating system kernel or other entity to which control is passed typically does not operate on the same data which the user application has been operating on. Thus, the data registers typically hold data values which are not useful to the new control entity but which must be maintained until the user application is resumed. The kernel must generally have registers for its own use, but typically has no way of knowing which registers are presently in use by the user application. In order to make space for its own data, the kernel must swap out or otherwise store the contents of a predetermined subset of the registers. This results in considerable loss of processing time to overhead, especially if the kernel makes repeated, short-duration assertions of control.
On a related note, in prior microprocessors, when it is required that a “grand scale” context switch be made, it has been necessary for the microprocessor to expend even greater amounts of processing r
Chen Sho Long
Garg Sanjiy
Lentz Derek J.
Nguyen Le Trong
Donaghue Larry D.
Seiko Epson Corporation
Sterne Kessler Goldstein & Fox P.L.L.C.
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