Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Identifying or correcting improper counter operation
Patent
1990-05-29
1991-10-22
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Identifying or correcting improper counter operation
377 55, 377 56, 377111, 377114, 377116, H03K 2140, H03K 2110
Patent
active
050602438
ABSTRACT:
An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.
REFERENCES:
patent: 3051855 (1962-08-01), Lee
patent: 3725791 (1973-04-01), Moreau et al.
patent: 4002926 (1977-01-01), Moyer
patent: 4493095 (1985-01-01), Yazawa
patent: 4512030 (1985-04-01), Fukuta
patent: 4726045 (1988-02-01), Caspell et al.
patent: 4891827 (1990-01-01), Slater
Heyman John S.
King Robert L.
Motorola Inc.
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