Boots – shoes – and leggings
Patent
1997-04-16
1999-05-04
Mai, Tan V.
Boots, shoes, and leggings
36471508, G06F 742, G06F 700
Patent
active
059010762
ABSTRACT:
A floating point arithmetic unit is provided which effectuates arithmetic operations upon floating point numbers. A comparator unit, which may be implemented using a carry-skip chain, determines the relative magnitudes of the exponents of the floating point numbers to be operated upon. A first ripple carry subtractor unit formed within a first ripple carry shifter subtracts a first value corresponding to the exponent of a first of the floating point numbers from a second value corresponding to the exponent of a second of the floating point numbers. A second ripple carry subtractor unit formed within a second ripple carry shifter subtracts the second value from the first value. When certain lower order bit results of the exponent value subtraction operations of each ripple carry subtractor are obtained, the mantissa of the floating point number with the smaller exponent provided to one of the carry ripple shifters is shifted to the right by a number of positions dependent upon the lower order bit results. Effectuation of this shift operation begins before determining certain intermediate order and high order bit results of the subtraction operation. When certain intermediate bit results of the exponent subtraction operation are obtained, further shifting of the mantissa is effectuated before the highest order bit results of the subtraction operation are determined. A final shift operation is effectuated upon determining the highest order bit results of the ripple carry subtraction operation. An output signal from the comparator unit, which determines the relative magnitudes of the exponents of the two floating point numbers being operated upon, selects the shifted mantissa output from the ripple carry shifter associated with the mantissa of the floating point number with the smaller exponent. This shifted mantissa is provided to an input of an adder/subtractor unit.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 4999800 (1991-03-01), Birger
patent: 5016209 (1991-05-01), Ikeda et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5166898 (1992-11-01), Ishihara
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
Intel, "Chapter2: Microprocessor Architecture Overview," pp. 2-1 through 2-4, undated.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
Advanced Micro Designs, Inc.
Kivlin B. Noel
Mai Tan V.
LandOfFree
Ripple carry shifter in a floating point arithmetic unit of a mi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ripple carry shifter in a floating point arithmetic unit of a mi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ripple carry shifter in a floating point arithmetic unit of a mi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1874619