Ripple carry logic ASND method

Details Ripple carry logic ASND method Ripple carry logic ASND method

1997-04-28

1998-06-09

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

377 78, 327269, 327270, 327361, G11C 1900

Patent

active

057647186

ABSTRACT:
Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage. Similarly, output registers for latching the logic output of each bit-level logic stage are clocked at successively delayed intervals substantially equal to the processing delay interval, and carry output signals from preceding logic stages are supplied to carry inputs of successive logic stages without additional delays following the processing delay interval of each preceding logic stage.

REFERENCES:
patent: 5481582 (1996-01-01), Ibenthal
patent: 5488318 (1996-01-01), Vajapey et al.

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