Ring topology for an integrated circuit logic cell

Details Ring topology for an integrated circuit logic cell Ring topology for an integrated circuit logic cell

1985-11-27

1988-04-12

Edlow, Martin H.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 231, 357 41, 357 45, 357 15, 357238, 307304, 307448, 307468, H01L 2702, H01L 2978, H01L 2948, H03K 19017

Patent

active

047378379

ABSTRACT:
An improved topology for a multi-input Boolean logic circuit whereby the circuit can be realized in integrated circuit form while consuming less area on the semiconductor wafer and exhibiting lower parasitic capacitance than equivalent integrated circuits using conventional topology. Rather than employing what might be described as an "in-line" topology of the prior art, a ring topology is used wherein adjacent MESFET's share a common region for source, drain, or source/drain contacts and wherein the amount of second level interconnect required is minimized.

REFERENCES:
patent: 3406298 (1968-10-01), Axelrod
patent: 3969745 (1976-07-01), Blocker, III
patent: 3995174 (1976-11-01), Zrudsky
patent: 4079408 (1978-03-01), Kwap et al.
patent: 4152714 (1979-05-01), Hendrickson et al.
patent: 4315272 (1982-02-01), Vorhaus
patent: 4322738 (1982-03-01), Bell et al.
patent: 4566022 (1986-01-01), Kalter et al.

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