Ring oscillator with embedded scatterometry grate array

Details Ring oscillator with embedded scatterometry grate array Ring oscillator with embedded scatterometry grate array

2003-01-22

2004-10-05

Kinkead, Arnold (Department: 2817)

Oscillators

Ring oscillators

C438S008000, C438S015000, C356S341000, C356S237400

Reexamination Certificate

active

06801096

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to a metal-oxide-semiconductor (MOS) ring oscillator with an embedded scatterometry grate array. Scatterometry measurements can then be used to control processes for forming lines of the ring oscillator, and for forming semiconductor devices incorporating the ring oscillator.
BACKGROUND OF THE INVENTION
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor. Types of MOS transistors include NMOS, PMOS and CMOS transistors. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
Typically, integrated circuit devices are comprised of millions of transistors formed above a semiconducting substrate. The semiconducting substrate or wafer is comprised of doped-silicon, doped with either N-type or P-type dopant materials. The transistor, for example, has a doped polycrystalline silicon (polysilicon) gate electrode formed above a gate insulation layer. The gate electrode and the gate insulation layer are separated from doped source/drain regions of the transistor by a dielectric sidewall spacer. The source/drain regions for the transistor may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g. arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate. Shallow trench isolation regions are provided to isolate the transistor electrically from neighboring semiconductor devices, such as other transistors. Additionally, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate.
Standard digital logic circuit performance can be generalized relatively effectively by ring oscillator frequency. Processors formed from thousands and millions of transistors on a die normally include at least one ring oscillator circuit for providing frequency synthesis. A conventional ring oscillator circuit comprises an odd number of inverter stages serially connected in a ring. In a conventional MOS transistor ring oscillator, each stage comprises a p-channel transistor and an n-channel transistor pair serially connected between first and second voltage potentials, typically a positive supply voltage and ground. The cannon terminal of the transistors is the output of the stage and is connected to the gates of the succeeding transistor pair. A capacitor shunts the output terminal to ground.
Semniconductor manufacturing generally involves multiple processes whereby multiple layers of material are formed above a semiconducting substrate, and portions of those layers are selectively removed until such time as a completed device is formed. These layers may be patterned using known photolithography and etching techniques. In general, photolithography involves the process of forming a layer of photoresist material above one or more process layers in which a feature, e.g., a metal line, a gate electrode, an opening in a layer of insulating material, will be formed. Thereafter, a pattern that is desired to be transferred into the underlying process layer or layers will be formed in the layer of photoresist material. Then, using one or more etching processes, the underlying process layer is etched using the patterned layer of photoresist as a mask, thereby resulting in a patterned process layer that replicates the pattern formed in the layer of photoresist.
One illustrative process flow for forming a portion of a transistor includes forming a process layer comprised of a gate insulation material, e.g., silicon dioxide, above the semiconducting substrate. Typically, this is accomplished by an oxidation process. Then, a process layer comprised of a gate electrode material, e.g., polysilicon, is formed above the process layer. The polysilicon layer may be formed by a variety of processes, e.g., by a chemical vapor deposition (“CVD”) process. If desired, an anti-reflective coating layer may also be formed above the polysilicon layer to reduce reflections during subsequent photolithography exposure processes. Me anti-reflective coating layer may be comprised of a variety of materials, e.g., silicon nitride, silicon oxynitride, etc. Thereafter, a patterned layer of photoresist material (positive or negative) is formed above the polysilicon layer using known photolithography techniques, and one or more etching processes will be performed to form
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gate electrode array from the polysilicon layer using the patterned layer of photoresist as a mask.
One problem encountered with existing processes used to form lines of the devices is controlling the widths of the lines. Line width control is very important in modem semiconductor manufacturing operations. For example, if a conductive line is made too narrow or too wide, then the resistance of the line will be wrong and the line will not conduct the amount of charge that it is designed to conduct. Previously, the width of various device lines has been measured by a variety of metrology tools, such as an ellipsometer, a reflectomer, a spectrometer, or some combination thereof. These tools tend to work well for measuring flat, uniform thin films, but many modern semiconductor manufacturing processes depend less upon uniform film thickness than surface topography or profile of the process layer and device lines.
What is still desired is a new and improved metrology apparatus and method that may provide a more robust technique for measuring or determining the topography or surface profile of a process layer and device lines. Preferably, the new and improved metrology apparatus and method can be incorporated into a common circuit, such as a MOS transistor ring oscillator so that line widths can be measured properly and in-situ during the manufacturing of the transistor.
SUMMARY OF THE INVENTION
This and other needs are met by embodiments of the present invention which provides a MOS ring oscillator that includes a number of serially connected inverter stages with each stage comprising a MOS transistor pair. At least one of the transistors also comprises a scatterometry grate array, which can then be used during manufacturing of the ring oscillator to obtain scatterometry measurements that allow polysilicon lines of the MOS ring oscillator to have widths of less than 60 nm.
Embodiments of the present invention also provide a method of manufacturing a MOS ring oscillator on a die that includes forming at least one grate array above a substrate, illuminating the grate array, measuring light reflected off of the grate array to generate an optical characteristic trace for the grate array, and comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a grate array having a desired profile. According to another embodiment, the method further includes depositing a process layer above the grate array, illuminating the process layer and the grate array, measuring light reflected off of the process layer and the grate array to generate an optical characteristic trace for the process layer and the grate array, and comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a process layer having a desired profile. According to a farther aspect the method also includes using line width measurements obtained from the grate ar

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