Ring oscillator with a digitally programmable frequency

Details Ring oscillator with a digitally programmable frequency Ring oscillator with a digitally programmable frequency

2002-10-11

2004-11-30

Kinkead, Arnold (Department: 2817)

Oscillators

Ring oscillators

C331S17700V

Reexamination Certificate

active

06825732

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to digital circuits. More specifically, the present invention relates to a method and an apparatus for digitally programming a frequency for a ring oscillator.
2. Related Art
Digital circuits typically operate under control of a system clock signal that is used to synchronize interactions between circuit elements. Because of the simplicity of its design, a ring oscillator is often used to generate such a clock signal.
A ring oscillator is comprised of an odd number of inverting stages connected into a ring. For example, referring to
FIG. 1
, ring oscillator
103
on semiconductor chip
102
includes five inverters
104
-
108
connected input-to-output to form a ring in which the output of the last inverter
108
feeds back into the input of the first inverter
104
.
Assuming that each inverting stage is identical, this circuit produces a clock signal that oscillates with a period equal to twice the gate delay of each inverting stage multiplied by the number of inverting stages. For example, if each of the five inverters
104
-
108
in
FIG. 1
has a one-nanosecond delay, ring oscillator
103
will oscillate with a period of 10 nanoseconds.
It is often useful to be able to dynamically change the clock frequency of a digital system. For example, the clock frequency can be decreased during latent periods of operation in order to decrease the power consumption of the digital circuit. Furthermore; it is often desirable to fine tune circuitry after fabrication to achieve a desired clock speed. Note that variations in the processes used to manufacture semiconductor chips often cause substantial variations in propagation delay through circuit elements. It is therefore not possible to determine how fast a digital circuit will operate before it is manufactured. Hence, it is typically necessary to fine tune a digital after it is manufactured to achieve a desired frequency.
A number of ring oscillator designs allow the number of inverting stages in the ring oscillator to be adjusted through fuses or semiconductor switches. For example, see U.S. Pat. No. 5,689,213, entitled “Post-Fabrication Programmable Integrated Circuit Ring Oscillator,” by inventor Joseph C. Sher, filed on Aug. 23, 1995 and issued on Nov. 18, 1997. However, in these designs, inverting stages must be added or removed from the ring oscillator in pairs. This means that only coarse frequency adjustments are possible using this technique.
Hence, what is needed is a method and an apparatus for adjusting the frequency of a ring oscillator without the problems listed above.
SUMMARY
One embodiment of the present invention provides a ring oscillator with a digitally programmable frequency. This ring oscillator includes an odd number of inverting stages coupled input to output to form a ring, and a programming mechanism configured to digitally program the drive strength for each inverting stage in the ring oscillator, thereby changing the propagation delay between inverting stages and thereby allowing the frequency of the ring oscillator to be adjusted.
In a variation on this embodiment, a given inverting stage includes a plurality of tri-state inverters coupled in parallel, so that inputs of the tri-state inverters are coupled to a common input for the given inverting stage, and outputs of the tri-state inverters are coupled to a common output for the given inverting stage. Moreover, each of the tri-state inverters can be selectively enabled, thereby allowing the drive strength of the given inverting stage to be adjusted.
In a further variation, the tri-state inverters for the given inverting stage have equal drive strength, so that enabling additional tri-state inverters increases the drive strength of the given inverting stage linearly.
In a further variation, the tri-state inverters for the given inverting stage have different gate lengths and hence different drive strengths.
In a further variation, the tri-state inverters for the given inverting stage have drive strengths that vary by powers of two, so that the drive strength of the given inverting stage can be digitally programmed with a binary number.
In a further variation, a tri-state inverter in the given inverting stage includes: a first P-type transistor with a source coupled to V
DD
, and a gate coupled to the input of the tri-state inverter; a second P-type transistor with a source coupled to the drain of the first P-type transistor, a gate coupled to an enable signal for the tri-state inverter and a drain coupled to the output of the tri-state inverter; a first N-type transistor with a drain coupled to the output of the tri-state inverter, and a gate coupled to the inverse of the enable signal; and a second N-type transistor with a drain coupled to the source of the first N-type transistor, a gate coupled to the input of the tri-state inverter and a source coupled to ground.


REFERENCES:
patent: 4517532 (1985-05-01), Neidorff
patent: 4988960 (1991-01-01), Tomisawa
patent: 5689213 (1997-11-01), Sher
patent: 6204694 (2001-03-01), Sunter et al.
patent: 6272439 (2001-08-01), Buer et al.
patent: 6359477 (2002-03-01), Pathak

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