Oscillators – Ring oscillators
Reissue Patent
1998-06-11
2001-04-03
Grimm, Siegfried H. (Department: 2817)
Oscillators
Ring oscillators
C331S10800D, C331S17700V, C327S278000, C327S281000, C327S285000, C327S288000
Reissue Patent
active
RE037124
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an oscillator and more particularly to a ring oscillator.
BACKGROUND OF THE INVENTION
New manufacturing processes and new applications are forcing power supplies to lower voltages (3.3 v now, with 2.4 v and 1.5 v being expected soon). Advanced Phase-Locked Loops require stable oscillators which may be varied in frequency by a control signal.
To help achieve frequency stability, oscillators integrated into a noisy VLSI environment often use a regulator to generate a quiet power supply. This usually has to be at an even lower voltage than the normal power supply.
There is thus a desire to provide oscillators which can work at these very low supply voltages and still produce high quality, high frequency output signals.
Reference is made to IBM Technical Disclosure Bulletin, Vol. 31, No. 2, July 1988, pages 154 to 156 “CMOS Ring Oscillator with controlled frequency” which describes a ring oscillator using CMOS transistors and is designed to give an almost sinusoidal output. This design suffers from stability problems outside a narrow range of frequencies. In particular, as the frequency increases, the amplitude decreases and it becomes difficult to convert the signal to CMOS levels.
SUMMARY OF THE INVENTION
According to the present invention there is provided a ring oscillator comprising a plurality of oscillator stages, each stage comprising a first and second transistors. The first transistor has a controllable path connected between an output node and a reference voltage and a control node acting as an input node to the stage. The second transistor has a controllable path connected between the output node and the reference voltage and a control node connected to the output node. The gain of each stage is selectively determined by the ratio of the widths of the first and second transistors to produce an output signal having a sawtooth or trapezoidal waveform. Each stage further comprise a respective current source which controls the speed of the stage and which is connected to the output node. The input node of one stage is connected to the output node of a preceding stage to form a ring and the number of stages is selected so that there is a total phase shift of 360° around the ring at the frequency of operation.
For transistors of the same length, the width of the first transistor can be set to m times the width of the second transistor where m>1 to determine the d.c. gain of the stage. This ratio m determines the shape of the waveform output by the oscillator. The higher the value of m, the more the waveform moves away from a sinusoid. For a three stage oscillator, a ratio of m close to 2 produces a substantially sinusoidal output. The present invention uses a ratio higher than 2 and preferably with a minimum value of 2.5. In practice the smallest value that can be selected to provide an appropriately shaped waveform will be selected. The maximum value of m is limited by practical considerations and particularly layout considerations. A practical maximum value for m is likely to be about 10.
The first and second transistors can be n-channel field effect devices having a gate as the control node and the source-drain path as the controllable path. As the transistors are of the same type, process variations affect the transistors in the same manner. The maximum frequency of operation is limited only by the ratio of gain to gate capacitance.
The current source can comprise a p-channel transistor gated by a control voltage.
The first transistor is preferably operated in its saturation region.
The current sources of each stage can either be controlled by a common control signal or by respective different control signals.
The present oscillator can operate at voltages down to a level just above the threshold voltages of the transistors.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.
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Bennett et al., “Sub-Nanosecond Bipolar LSI”1stI.E.E. European Solid State Circuits Conference,London, GB, pp. 34-35, 1975.
IBM Technical Disclosure Bulletin,32:(12), pp. 149-151, May 1990.
IBM Technical Disclosure Bulletin,31:(2), pp. 154-156, Jul. 1988.
Kumar, U. and S.P. Suri, “A simple digital 2nfrequency multiplier,”Int. J. Electronics48:(1), pp. 43-45, 1980.
McGahee, T., “Pulse-frequency doubler requires no adjustment,”Electronics48:(8), p. 149, Apr. 17, 1975.
Ware, et al., “THPM 14.1: a 200 MHz CMOS Phase-Locked Loop With Dual Phase Detectors,”IEEE International Solid-State Circuits Conference,New York, USA, pp. 192-193 and 338, 1989.
Hall Andrew M.
Monk Trevor K.
Galanthay Theodore E.
Grimm Siegfried H.
Seed IP Law Group PLLC
STMicroelectronics Limited
Tarleton E. Russell
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