Oscillators – Ring oscillators
Reexamination Certificate
2001-12-20
2003-11-04
Pascal, Robert (Department: 2817)
Oscillators
Ring oscillators
C331S17700V
Reexamination Certificate
active
06642802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to radiation-hardened circuitry. More particularly, this invention is an oscillator capable of maintaining output signal integrity in the presence of transient signals caused by radiation.
2. Description of the Background Art
Electronic systems deployed in outer space or orbital environments may be subject to bombardment by high-energy particles, for example, protons, alpha particles, and/or other types of cosmic rays. Such high-energy particles may induce signal errors and possibly damage circuitry. For example, during periods of high solar flare activity, or in orbital regions characterized by radiation belt anomalies, high-energy particle bombardment may render communication satellites temporarily or permanently unreliable.
When a high-energy particle impinges upon an integrated circuit, it ionizes the regions through which it travels. This ionization creates mobile charges in the vicinity of the particle's travel path, thereby generating a transient signal or pulse in the device. A transient pulse so generated may be referred to as a Single Event Transient (SET), and may produce a Single Event Upset (SEU), which is a random, soft (i.e., nondestructive) logic or signal error. An SEU may change critical data and/or alter program or processor state. Depending upon severity, a circuit, device, or system may require a power reset to recover from an SEU.
A variety of approaches for reducing or minimizing SET and/or SEU susceptibility exist. Special integrated circuit fabrication techniques, such as Silicon-on-Insulator (SOI) processes, may reduce SEU susceptibility. However, special fabrication techniques are significantly more costly than standard integrated circuit manufacturing processes.
An SEU is less likely to occur if the magnitude of its associated transient pulse is significantly less than the magnitude of normal signals within a device. Larger devices generally operate using larger-magnitude signals. Hence, another way to minimize SEU susceptibility is through the use of large-area devices. Unfortunately, large-area circuitry is less area-efficient, necessitates higher manufacturing costs, and consumes more power than densely packed circuitry. As a result, large area circuitry suffers from significant drawbacks relative to outer space or orbital applications.
Another approach to reducing SEU susceptibility is known as Triple Modular Redundancy (TMR), which involves replicating independent logic gates or stages three times. Each stage provides an output to a voting circuit, which determines a final output state as that which is output by a majority of the stages. The redundancy that TMR requires unfortunately results in drawbacks similar to those for large-area circuitry.
Yet another approach toward minimizing SEU susceptibility is circuit design modification. Such modification involves duplication of storage elements and provision of state-restoring feedback paths.
FIG. 1
is a circuit diagram of an SEU immune storage cell that includes state-restoring feedback paths. The SEU immune storage cell may serve as a latch or flip flop, or an element within a memory.
Unfortunately, prior circuit design modifications for minimizing SET and/or SEU susceptibility are generally directed toward sequential, latching, and/or storage elements. What is needed is an architecture that provides SET and/or SEU immunity to other types of circuitry with minimal circuit redundancy, and which may be manufactured using conventional integrated circuit fabrication techniques.
SUMMARY OF THE INVENTION
The present invention is a ring oscillator that may provide SET immunity. In one embodiment, the ring oscillator comprises a dual path ring oscillator core coupled to a set of dual path inverters followed by a dual to single path converter. The dual path ring oscillator core may itself comprise three or more dual path inverters, each of which includes a first inverter providing a first output and a second inverter providing a second output.
Within the first inverter of any particular dual path inverter, a first transistor or current control element is coupled to a first output of a previous dual path inverter, while a second transistor or current control element is coupled to a second output of the previous dual path inverter. Similarly, within the second inverter of the given dual path inverter, a first transistor or current control element is coupled to the second output of the previous dual path inverter, while a second transistor or current control element is coupled to the previous dual path inverter's first output. A first dual path inverter maintains couplings to a final dual path inverter in an analogous manner. The aforementioned interleaved couplings ensure that if a transient pulse affects a circuit node within the dual path ring oscillator core, at least one inverter within a dual path inverter coupled to the circuit node outputs or maintains a correctly valued signal, and the transient pulse will not propagate through a successive dual path inverter stage.
In the absence of a transient pulse, the signals that a dual path inverter asserts at its first and second outputs at any given time correspond to identical values or logic states. Hence, the input signals applied to a subsequent dual path inverter are identically valued in the absence of a transient pulse. Within a dual path inverter coupled to receive signals from a circuit node affected by a transient pulse, only a subset of transistors or current control elements within the first and second inverters are affected, because other transistors or current control elements are coupled to receive signals from an unaffected circuit node. In the event that the transient pulse causes the first inverter within the dual path inverter to temporarily experience a state of contention, for example, the second inverter within the dual path inverter may hold or maintain an output signal at its most recent, correct value as a result of stray capacitance at its output node.
The dual to single path converter includes inputs and an output, and may be coupled to receive signals produced by the final dual path inverter within the dual path oscillator core. In one embodiment, the dual to single path converter comprises a first inverter structure that is embedded within a current path of a second inverter structure. The first inverter structure may be coupled to receive a first output provided by the dual path oscillator core's final dual path inverter, while the second inverter structure may be coupled to receive a second output provided by the dual path oscillator core's final dual path inverter. An output of the dual to single path converter may be provided by the first inverter structure.
When the dual to single path converter receives identically valued input signals, both inverter structures are in an identical operational state, and thus the dual to single path converter asserts an output signal having a correct or desired value. A transient pulse may cause a signal applied to an input of the dual to single path converter to experience a transition of sufficient magnitude to cause the inverter structure to which it is coupled to switch to an opposite operational state. As a result, current flow within or through the dual to single path converter may be temporarily interrupted. During this temporary interruption, the stray or parasitic capacitance present at the dual to single path converter's output node maintains the output signal in its most recent state. In one embodiment, the dual to single path converter corresponds to a Muller C-element.
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U.S. patent application Ser. No. 09/854,247, Knowles, filed May 11, 2001.
T. Calin, et al., Upset Hardened Memory Design For Submicron CMO
Knowles Kenneth R.
Thoma Nandor G.
BAE Systems Information and Electronic Systems Integration Inc.
Graybeal Jackson Haley LLP
Long Daniel J.
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