Ring oscillator having variable coarse and fine delays

Details Ring oscillator having variable coarse and fine delays Ring oscillator having variable coarse and fine delays

1999-12-17

2001-07-10

Grimm, Siegfried H. (Department: 2817)

Oscillators

Ring oscillators

C331S17700V

Reexamination Certificate

active

06259330

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a ring oscillator having a variable delay and, more particularly, to a ring oscillator having a variable delay suitably used for a digital phase locked loop (PLL) circuit.
(b) Description of a Related Art
A ring oscillator having a variable delay (delay time) is generally used in a digital PLL circuit as a voltage controlled oscillator (VCO).
A Patent Publication JP-A-6-77782 describes a conventional ring oscillator having a variable delay, wherein the oscillation frequency range and the gain of the ring oscillator can be controlled. The ring oscillator includes a plurality of delay gates cascaded in a ring fashion. The delay gates are provided with a first control block for controlling the oscillation frequency of the delay gates at a coarse delay step by controlling the applied voltage or operational current of the delay gates. A second control bock is also provided for controlling the oscillation frequency of at least one of the delay gates at a fine delay step. By these configurations, the gain control separately from the oscillation frequency is possible in the ring oscillator, whereby fine control for the oscillator frequency can be effected. The second control block has fixed adjustment steps in the fine delay control.
The delay (delay time) of the ring oscillator largely affects the jitter characteristic of the digital PLL circuits, as in the case of the ring oscillator described in the above embodiment. The delay can be generally designed in the ring oscillator by using a simulation. However, it is difficult to compensate variations of delay of the ring oscillator caused by the fabrication process thereof between chips in a wafer or between lots or variations caused by environmental conditions of the ring oscillator. That is, the design for compensation of the variations at least increases the design steps for the ring oscillator, and yet effective compensation for the variations is difficult to achieve in the digital PLL circuit.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a ring oscillator which is capable of suppressing the adverse effects in a PLL circuit caused by the variations of the fabrication process and variations by the environmental conditions for the ring oscillator.
In one embodiment of the present invention, the ring oscillator includes a coarse delay control block including a plurality of coarse delay gates each effecting a first delay, a fine delay control block including a plurality of fine delay gates each effecting a second delay, the coarse delay control block and the fine delay control block being connected in a feed-back loop for effecting an overall delay of the ring oscillator, the first delay being larger than the second delay and smaller than a total of the second delays in the fine delay control block.
In accordance with the ring oscillator of the present invention, since the total delay of the fine delay control block is made larger than the delay step of the coarse delay control block, the maximum overall delay step of the ring oscillator is not larger than the second delay of the fine delay control block even if the variations of the first delay or second delay occur. Thus, the jitter characteristic of a PLL circuit having the ring oscillator of the present invention can be improved.
In the conventional ring oscillator, there is a problem in that the variations of the first delay or the second delay due to variations in the fabrication process may increase the first delay or may reduce the second delay step so that the total of the second delays is lower than the first delay. In this case, the variations generate a larger delay step at the shift stage of the ring oscillator when the ring oscillator shifts the delay step of the coarse delay control block by one step, whereby the oscillator frequency fluctuates at the shift stage and a problem jitter is involved.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.


REFERENCES:
patent: 5382921 (1995-01-01), Estrada et al.
patent: 5691669 (1997-11-01), Tsai et al.
patent: 2-210908 (1990-08-01), None
patent: 4-286417 (1992-10-01), None
patent: 5-259844 (1993-10-01), None
patent: 6-77782 (1994-03-01), None

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