Oscillators – Ring oscillators
Reexamination Certificate
2003-04-29
2004-10-26
Kinkead, Arnold (Department: 2817)
Oscillators
Ring oscillators
C331S175000, C331S176000, C331S185000
Reexamination Certificate
active
06809603
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a ring oscillator. In particular, the present invention discloses a ring oscillator whose output signal is not affected by the characteristics of MOS devices.
2. Description of the Prior Art
In modern information society, a digital system capable of processing digital data needs a clock signal to arbitrate and coordinate timings associated with processing and transmission of the digital data. Therefore, an oscillator used to generate the required clock signal becomes a fundamental component in a modern digital circuit. In addition, a phase lock loop (PLL) of signal processing circuits used in a general communication system, an optical disk drive, and a hard-disk drive commonly applies a voltage-controlled oscillator (VCO). That is, voltages are used to control a voltage-controlled oscillator to make the clock signal have a specific period or a specific frequency. With the improvement of transmission and processing speeds for digital signals, it becomes an important issue to manufacture oscillators that are capable of generating high-frequency (short period) clock signals.
Please refer to
FIG. 1
, which is a diagram of a prior art ring oscillator
10
. The ring oscillator
10
has a plurality of delay cells cascaded to form a closed loop. Please note that only three delay cells
12
a
,
12
b
,
12
c
are shown in
FIG. 1
for simplicity. Operation of the delay cells
12
a
,
12
b
,
12
c
are similar to that of an inverter, and functionality of the delay cells
12
a
,
12
b
,
12
c
are to make input ports IP
1
, IP
2
, IP
3
and related output ports OP
1
, OP
2
, OP
3
correspond to opposite voltage levels. For example, when the input port IP
1
corresponds to a high voltage level, the corresponding output port OP
1
corresponds to a low voltage level; on the other hand, when the input port IP
1
corresponds to the low voltage level, the corresponding output port OP
1
corresponds to the high voltage level.
Operation of the ring oscillator
10
is described as follows. When the input port IP
1
of the delay cell
12
a
corresponds to the high voltage level, the output port OP
1
of the delay cell
12
a
corresponds to the low voltage level. Because the output port OP
1
of the delay cell
12
a
is electrically connected to input port IP
2
of the following delay cell
12
b
, the input port IP
2
of the delay cell
12
b
, therefore, corresponds to the low voltage level. The output port OP
2
of the delay cell
12
b
then corresponds to the high voltage level. Similarly, because output port OP
2
of the delay cell
12
b
is electrically connected to input port IP
3
of the following delay cell
12
c
, the input port IP
3
of the delay cell
12
c
corresponds to the high voltage level for driving output port OP
3
of the delay cell
12
c
to correspond to the low voltage level.
It is noteworthy that output port OP
3
of the delay cell
12
c
is electrically connected to the input port IP
1
of the delay cell
12
a
, and the input port IP
1
initially corresponds to the high voltage level. However, the closed loop formed by the delay cells
12
a
,
12
b
,
12
c
forces the input port IP
1
of the delay cell
12
a
to correspond to the low voltage level after the delay cells
12
a
,
12
b
,
12
c
sequentially operate. After input port of each delay cell
12
a
,
12
b
,
12
c
receives an input signal, the corresponding delay cell requires a delay time Td to generate an output signal having a voltage level opposite to that of the input signal. Therefore, voltage level at the output port and input port of each delay cell
12
a
,
12
b
,
12
c
has a level transition every three delay time 3*Td.
The level transition means that the voltage level transits from the original high voltage level to the low voltage level or the voltage level transits from the original low voltage level to the high voltage level. In other words, the period of the clock signal F
0
generated from the ring oscillator
10
becomes 6*Td. In addition, the control voltage Vc is used to adjust the delay time of each delay cell
12
a
,
12
b
,
12
c
. Therefore, period of the clock signal F
0
is controllable with the adjustment of the voltage value of the control voltage Vc.
Please refer to
FIG. 2
, which is a diagram of the delay cell
12
a
shown in FIG.
1
. The delay cell
12
a
includes a plurality of p-channel metal oxide semiconductor (PMOS) transistors
14
a
,
14
b
, and a plurality of n-channel metal oxide semiconductor (NMOS) transistors
16
a
,
16
b
. The transistors
14
a
,
14
b
,
16
a
,
16
b
are fabricated according to a CMOS semiconductor process. The transistors
14
a
,
16
a
are matched to correspond to the same transistor characteristics such as an identical doping concentration, an identical channel width/length ratio, etc. In addition, the transistors
14
b
,
16
b
are matched as well.
The transistors
14
a
,
16
a
function as current sources. That is, the transistors
14
a
,
16
a
operate in a saturation region. Therefore, when a control voltage V
c1
is inputted into a gate of the transistor
14
a
, a fixed reference current I
1
flowing from a voltage source Vdd (high voltage level) toward the transistor
14
b
is generated. Similarly, when a control voltage V
c2
is inputted into a gate of the transistor
16
a
, a fixed reference current I
2
flowing from the transistor
16
b
toward a voltage source Vss (low voltage level) is generated.
Operation of the delay cell
12
a
is briefly described as follows. If the input port IP
1
corresponds to a high voltage level, the transistor
16
b
is turned on, and the transistor
14
b
is turned off. Therefore, the reference current I
2
starts discharging the output port OP
1
to make the output port OP
1
correspond to the low voltage level.
As mentioned above, when the delay cell
12
c
operates, the level transition occurs at the input port IP
1
of the delay cell
12
a
. Therefore, after the voltage level of the input port IP
1
transits from the high voltage level to the low voltage level, the transistor
14
b
is turned on, and the transistor
16
b
is then turned off. The reference current I
1
, therefore, begins charging the output port OP
1
to make the output port OP
1
correspond to the high voltage level. In other words, the transistors
14
b
,
16
b
function as switches used to determine that the output port OP
1
needs to be charged or discharged according to the voltage level of the input port IP
1
. Then, the voltage levels of the output port OP
1
and the input port IP
1
correspond to opposite voltage levels.
In addition, the magnitudes of the reference currents I
1
, I
2
affect the delay time Td of the delay cell
12
a
. If the reference current I
1
is increased, the reference current I
1
raises the voltage level of the output port OP
1
much quicker. Similarly, if the reference current I
2
is increased, the reference current I
2
decreases voltage level of the output port OP
1
much quicker. Please note that the magnitudes of the reference currents I
1
, I
2
are dominated by the control voltages V
c1
, V
c2
. As shown in
FIG. 1
, the control voltage Vc generating the control voltages V
c1
, V
c2
is then capable of adjusting the delay time Td to alter period of the clock signal F
0
.
However, with regard to the transistors
14
a
,
16
a
, the transistor characteristics varies with the operating temperature, voltage sources Vdd, Vss, etc. For instance, when the operating temperature increases, mobility of electrons in the transistors
14
a
,
16
a
is suppressed. Therefore, under the same gate-to-source bias, current values of the reference currents I
1
, I
2
decrease owing to an increase of the operating temperature. On the other hand, when the operating temperature decreases, mobility of the electrons in the transistors
14
a
,
16
a
is improved. Therefore, under the same gate-to-source bias, current values of the reference currents I
1
, I
2
increase owing to a decrease of the operating temperature. In other words, if the oper
e-Memory Technology, Inc.
Kinkead Arnold
Winston Hsu
LandOfFree
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