Ring oscillator design for MOSFET device reliability...

Details Ring oscillator design for MOSFET device reliability... Ring oscillator design for MOSFET device reliability...

2000-06-22

2002-11-05

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06476632

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to ring oscillators (RO) and, more particularly, to an RO that allows parallel stressing of MOSFET devices in each of its inverter stages under any set of DC or AC voltage bias conditions.
BACKGROUND OF THE INVENTION
In recent years, the information technology industry has experienced an extremely rapid growth thanks to the availability in the market of semiconductor chips with larger density, higher performance and more complex chip functions availability. One of the main contributors to this growth is the recent advance in deep sub-micron CMOS technology development. To meet the requirements of high performance microprocessors (i.e., 1 Ghz and above), the storage capacity of advanced DRAMs (1 Gbit and above) as well as the large function complexity of chips such as EDRAM or SOC, there is a need for more aggressive CMOS transistor devices. New NMOSFET and PMOSFET features have been introduced at a very fast rate. MOSFETs having a very thin gate oxide and different gate oxide processes such as nitride or deuterate oxides have been implemented. Aggressive shallow junction drain engineering such as LDD, extension and halo implants have helped to reduce the short channel effects that otherwise will be experienced, which may limit the use of deep sub-micron MOSFETs (less than 0.1 um).
An important element affecting the applicability of a given sub-micron CMOS technology to the aforementioned chip requirements is its level of reliability. In particular, it is considered critical to ensure that fundamental MOSFET device wear-out mechanisms such as hot carrier (HC) or negative bias temperature instability (NBTI) are not a limiting factor when shrinking the transistor size. This concern has prompted, among others, a big effort in technology reliability to carefully quantify the tradeoff between chip performance and MOSFET device reliability. Special focus has been given to better evaluate the link between the results of the device reliability DC stresses, typically run during the technology qualification activities and the expected end of life chip performance degradation due to the activation of possible MOSFET wear-out mechanisms. The need of reducing the technology qualification cycles to meet aggressive market demands has also forced the introduction of wafer level reliability (WLR) methodologies, mainly to quickly characterize these MOSFET reliability failure mechanisms providing the same level of confidence as in standard technologies qualification methodologies.
Conventional Ring Oscillators (RO) are simple circuits formed by an odd prime number of CMOS inverters connected in cascade to form a loop. The odd prime number of inverters in series allows the output signal of the RO to oscillate (“ring”) between the power supply rail Vdd and the ground rail Vcc. Each inventor consists of two enhancement-mode MOSFET transistors, respectively, a pull-down NMOSFET transistor and a pull-up PMOSFET transistor. The ringing frequency depends on the output junction/capacitance load (fan-out) of each inverter stage, as shown in the conventional RO circuit illustrated in FIG.
1
. The RO frequency has been traditionally considered an effective vehicle for monitoring the dependence of the chip performance on the MOSFET design used as well as on the fan-out loading scheme simulating the output RC of the circuit.
Since the RO frequency increases with an increasing Vdd, it possible to stress a typical RO circuit by applying a sufficiently large Vdd. At high Vdd bias conditions, the high frequency periodic oscillations will accelerate the degradation of both the NMOSFET and PMOSFET devices in each inverter stage and the subsequent degradation of the RO frequency. Several works, for example, have reported a correlation between the NMOSFET device degradation of the drain current in saturation conditions and the RO frequency degradation during RO stressing by high frequency ringing.
A challenging outcome of the MOSFET down scaling is that the aggressive MOSFET device design and process used in sub-micron technologies activate new device degradation mechanisms that were not observed in the past. This finding limits the applicability of traditional RO designs as stress vehicles to characterize the link between the required chip performance, parameterized by the RO frequency degradation, and MOSFET reliability wear-out mechanisms, investigated at DC conditions, in deep sub-micron technologies.
With standard RO designs it is only possible to measure the cumulative contribution of all possible device degradation mechanisms which are activated during an RO periodic waveform to the RO frequency degradation. Standard RO designs, in fact, make it possible to investigate the RO frequency degradation dependence on periodic RO voltage waveforms. It has been found in previous LSI CMOS technologies (0.25 um ground rule and above) that this frequency degradation was due to hot carrier worst case degradation during AC transients which correspond to a peak substrate current (Isx) condition for the NMOSFET, which damage is controlled by interface states generation, and a peak gate current (Igate) condition for the PMOSFET, which damage is controlled by electron trapping, as shown in prior art
FIGS. 2 and 3
. It is, however, not easy to decouple the contribution of each failure wear-out activated during the AC waveform to the RO frequency degradation.
Additionally, because all ROs generate only AC periodic waveforms, typical RO circuits do not allow to quantify and isolate the impact to the RO frequency degradation from other possible device degradation mechanisms, that are not activated by periodic voltage waveforms, but which are possible contributors to the performance degradation in real circuits.
A simple example of this situation is shown by the circuit described in FIG.
4
. The circuit consists of an inverter stage (ISB) consisting of a PMOSFET device (PF) and a pair of NMOSFET devices (NF and NF
1
) in series. The gate of the NF
1
device is set to Vg=Vdd to ensure that this device is always on. With the input of the inverter stage (Vin) swinging between 0 and Vdd, its output (Vout) follows between Vdd and 0. Node C will swing between 0 and Vout−Vth(NF
1
), wherein Vth(NF
1
) is the Vth of the NF
1
device. Under these conditions the maximum Vds(NF) across NF is Vdd−Vth(NF
1
), while its maximum Vgs(NF) is Vdd.
The condition Vgs(NF) >Vds(NF) is possible in this situation, but it is not possible in the simple inverter scheme (IS) depicted in FIG.
5
. In the case shown, Vgs(NF) is always smaller or equal to Vdd. Because of the different relationship of Vgs(NF) relative to Vds(NS) for each of these inverters, the NMOSFET (NF) device in each inverter is expected to be sensitive to different degradation mechanisms. The NF device of the simple invert circuit (IS) is only sensitive to the interface states generation damage with Vgs=@ peak lsx (FIG.
5
), while the same device in the inverter circuit in
FIG. 4
(ISB) is sensitive to interface states generation with Vgs at peak Isx and electron trapping at Vgs(NF) >Vds(NF). The former damage produces channel mobility degradation, while the latter parasitic drain series resistance increases, as described in the article by S. K. Manhas et al, “Early stage hot carrier degradation of state of art Iss NMOSFETs”, IPRS 2000.
The frequency degradation of an RO consisting of cascaded inverter stages (IS) is controlled by the interface states generation damage taking place in NMSOFET device during the RO “ringing”, while the frequency degradation of an RO consisting of inverter stages (ISB) will have contributions from both the interface states generation as well as electron trapping. In the latter circuit, it is not possible to decouple the contribution of each mechanism to the RO frequency degradation. Therefore, it is not easy to quantify the individual contribution of each mechanism to the RO degradation. Thus, this illustrates an actual real circuit performance degradation t

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