Ring oscillator circuit and a delay circuit

Details Ring oscillator circuit and a delay circuit Ring oscillator circuit and a delay circuit

2002-05-20

2004-01-13

Kinkead, Arnold (Department: 2817)

Oscillators

Ring oscillators

C331S175000, C331S17700V, C327S266000, C327S274000

Reexamination Certificate

active

06677825

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Technology of the Invention
The present invention relates to ring oscillator circuits such as variable frequency type ring oscillator circuits and delay circuits such as variable delay circuits, and provides ring oscillator circuits with low power supply voltage dependency of the oscillation frequency and delay circuits with low power supply voltage dependency of the delay time.
2. Prior Art Technology
FIG. 5
is a diagram showing an example of a conventional variable frequency type ring oscillator circuit. In
FIG. 5
, Vin indicates a control voltage for controlling the oscillation frequency, and Sout an oscillation output.
The ring oscillator circuit comprises K units of inverter circuits U
21
, U
22
, . . . , U
2
K connected in a ring shape. In this instance, K is an odd number such as 3, 5, 7, . . . .
In
FIG. 5
, although the internal configurations of the inverter circuits U
22
, . . . , U
2
K are omitted except for the first-stage inverter circuit U
21
, all have the same circuit configuration as the first-stage inverter circuit U
21
.
The inverter circuit U
21
, as shown in
FIG. 5
, is equipped with a CMOS inverter IV
1
including a P-channel MOS transistor MP
4
and an N-channel MOS transistor MN
4
, and with a P-channel MOS transistor MP
3
and an N-channel MOS transistor MN
3
which function as the current source for the CMOS inverter IV
1
.
Specifically, the P-channel MOS transistor MP
4
has its gate terminal connected to an input terminal (IN) of the inverter circuit U
21
, its drain terminal connected to an output terminal (OUT) of the inverter circuit U
21
, and its source terminal connected to the power supply potential via the P-channel MOS transistor MP
3
. The N-channel MOS transistor MN
4
has its gate terminal connected to an input terminal (IN) of the inverter circuit U
21
, its drain terminal connected to an output terminal (OUT) of the inverter circuit U
21
, and its source terminal connected to the ground potential via the N-channel MOS transistor MN
3
.
The P-channel MOS transistor MP
3
and N-channel MOS transistor MN
3
that function as the current source for the CMOS inverter IV
1
are configured so that their current values can be varied by a control voltage Vin. This configuration is explained below.
Namely, an N-channel MOS transistor MN
1
forms a source follower and generates at both ends of a resistor R a voltage value which is approximately equal to the voltage (Vin−Vt) of the control voltage Vin with the threshold voltage Vt of the MOS transistor MN
1
subtracted. Hence, a current I
1
=(Vin−Vt)/R which varies according to the control voltage Vin flows in the N-channel MOS transistor MN
1
and the P-channel MOS transistor MP
1
.
The P-channel MOS transistors MP
1
and MP
2
constitute current mirrors. Hence, a current I
2
equal to the current I
1
also flows in the P-channel MOS transistor MP
2
and the N-channel MOS transistor MN
2
. Furthermore, the P-channel MOS transistors MP
1
and MP
3
, and the N-channel MOS transistors MN
2
and MN
3
also constitute current mirrors. Therefore, the P-channel MOS transistor MP
3
and the N-channel MOS transistor MN
3
both become a current source that outputs a current I
3
equal to the current I
1
.
An example of operations of a conventional variable frequency type ring oscillator circuit shown in
FIG. 5
is described next.
If a voltage signal at the “L” level is input to the input terminal (IN) of the inverter circuit U
21
, the P-channel MOS transistor MP
4
constituting a switching unit turns ON, the N-channel transistor MN
4
turns OFF, and a current I
3
is output from the output terminal (OUT). Conversely, if a voltage signal at the “H” level is input to the input terminal (IN) of the inverter circuit U
21
, the P-channel MOS transistor MP
4
turns OFF, the N-channel transistor MN
4
turns ON, and a current I
3
is drawn in through the output terminal (OUT).
The propagation delay time &tgr; of the inverter circuit U
21
is expressed by the following approximation formula:
&tgr;=
C
(
Vdd/
2)/
I
3
(1)
where C indicates the output capacitance of the inverter circuit U
21
, and Vdd the power supply voltage. Hence, the oscillation frequency f of the variable frequency type ring oscillator circuit in
FIG. 5
is given by the following equation:
f=
1/(2
K·&tgr;
)=
I
3
/(
K·C·Vdd
)(2)
where K indicates the number of connections of the inverter circuit.
Therefore, the ring oscillator circuit has a mechanism where the oscillation frequency f can be varied by making the current I
3
of the current source variable, namely by making the control voltage Vin variable.
FIG. 6
is a figure showing an example of conventional variable delay circuits. In
FIG. 6
, Sin indicates an input signal, and Sout a delay output signal.
As shown in
FIG. 6
, the delay circuit comprises K units of inverter circuits U
21
, U
22
, . . . , U
2
K connected in cascade.
In this instance, the delay circuit is completely the same with the variable frequency type ring oscillation circuit in a configuration other than the point that the output of the last-stage inverter circuit U
2
K is not fed back to the first-stage inverter circuit U
21
. Therefore, a detailed explanation is omitted.
In a delay circuit having such a configuration, because the propagation delay time &tgr; of the inverter circuit U
21
is given by the formula (1), its delay time t becomes as shown in the following formula:
t=K·&tgr;=K·C
(
Vdd/
2)/I
3
  (3)
Therefore, the delay circuit has a mechanism where the delay time t can be varied by making the current I
3
of the current source variable, namely making the control voltage Vin variable.
In conventional variable frequency type ring oscillator circuits and variable delay circuits, as stated earlier, the propagation delay time &tgr; of each inverter circuit is an amount proportional to the power supply voltage Vdd.
As the result, in a variable frequency type ring oscillator circuit, the oscillation frequency f varies in inverse proportion to the power supply voltage Vdd. Also, in a variable delay circuit, the delay time t varies in proportion to the power supply voltage Vdd.
Therefore, there has been an inconvenience with conventional variable frequency type ring oscillator circuits and conventional variable delay circuits in that a fluctuation occurs to the oscillation frequency f or delay time t if the power supply voltage Vdd varies along with the operations of the peripheral circuit.
Hence, if a variable frequency type ring oscillator circuit is used in a PLL (phase locked loop) or if a variable delay circuit is used in a DLL (delay locked loop) for example, the phase of the signal fluctuates due to a variation of the power supply voltage Vdd, decreasing the operation reliability of any system using these circuits.
The first objective of the present invention is to provide a ring oscillator circuit that can reduce the power supply voltage dependency of the oscillation frequency.
Also, the second objective of the present invention is to provide a delay circuit that can reduce the power supply voltage dependency of the delay time.
SUMMARY OF THE INVENTION
In order to overcome these problems and to achieve the first objective of the present invention, the inventions described in claim
1
-claim
4
are configured as follows.
The invention described in claim
1
is a ring oscillator circuit comprising an odd number of inverter circuits connected in a ring shape. The inverter circuit contains a first switching unit which includes at least two MOS transistors, a current source for the first switching unit, and the second switching unit which is installed in parallel to the first switching unit and includes at least two MOS transistors. The first switching unit and the second switching unit have their input terminals in a common connection and their output terminals in a common connection.
The invention described in claim
2
is a ring oscillator circuit comprising an odd number of inverter circuits connected i

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