Ring counters with synchronously controlled counting flip-flops

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307223R, 307224R, H03K 2102, H03K 2304

Patent

active

039493113

ABSTRACT:
A ring counter has a plurality of synchronously controlled counting flip-flops. Each of the flip-flops are constructed as a masterslave flip-flop with a majority decision input circuit with three input variables. An even number of the counting flip-flops, which operate in accordance with the Boolean equation Qtl = S . R + Qto . (S + R) are ring connected by way of their set inputs and the outputs associated with the set inputs. The reset inputs of the counting flip-flops of an even order, and of an uneven order, are connected with first and second control lines, respectively, for receiving counting information and negated counting information, respectively. The counting information for the first counting flip-flop is supplied and emitted with inversion. A binary divider controlled by counting pulses is connected to the first control line and its output information signals reach the first control line directly as counting information, while at the same time the counting information is supplied in an inverted form to the second control line. The ring counters are constructed very simply in an advantageous manner. Dynamic rectangular signals can be processed as counting pulses and their logical values are respectively provided by their phase position. If counting pulses are utilized having a logical value which is given by the respective signal amplitude, only one additional inverter must be provided with each counting flip-flop. Advantageously, the ring counters can be utilized for different signal shapes as counting pulses.

REFERENCES:
patent: 3105195 (1963-09-01), Hornoch
patent: 3798554 (1974-03-01), Sadlack
patent: 3811092 (1974-05-01), Charbonnier

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