Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including passive device
Patent
1997-09-29
1999-02-09
Bowers, Charles
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including passive device
438330, 438309, 438324, 438329, 438338, 438342, H01L 21328
Patent
active
058693815
ABSTRACT:
Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor structure having a small surface area to minimize parasitic capacitance, whereby resistor and capacitor surface areas of 100 square micrometers or less are obtained. Another feature of the invention is the use of a high dielectric material in realizing a resistor-capacitor impedance zero at a frequency much lower than the operating frequency of the transistor. For an operating frequency of 2 GHz and resistor values of 50-250 ohms, capacitance required is 3 pF or greater. Another feature of the invention is a method of fabricating the integrated resistive-capacitive element in either a low temperature process or a high temperature process which minimizes capacitor leakage when using a thin high dielectric insulative material between capacitor plates.
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Wolf Stanley, Silicon Processing for the VLSI Era, vol. 1, p. 520, 1990.
Hebert Francois
McCalpin William
Bowers Charles
Nguyen Thanh
Spectrian, Inc.
Woodward Henry K.
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