Amplifiers – With semiconductor amplifying device – Including field effect transistor
Reexamination Certificate
2000-02-18
2001-10-02
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including field effect transistor
C330S302000, C330S307000, C257S203000, C257S365000, C257S368000, C257S664000, C257S773000, C257S784000, C257S786000
Reexamination Certificate
active
06297700
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to RF power transistors, and more particularly the invention relates to improving performance of an RF transistor having multiple cascaded transistor cells by reducing phase offsets between the cells.
A power transistor typically comprises a plurality of transistor cells or unit elements in a semiconductor die with the cells connected in parallel for amplifying an input signal.
FIG. 1
is a plan view of a conventional power transistor in a semiconductor die
10
and including a plurality of cells
12
. For an LDMOS transistor, each cell includes a plurality of interdigitated drain
14
and gate
16
elements with wire bonding pads
18
and
20
respectively connected to drains
14
and gate
16
through metallization
22
and
24
as shown in FIG.
2
.
FIG. 3
is a schematic of the LDMOS transistor cell in which the source comprises the grounded semiconductor substrate, and
FIG. 4
is a section view of one LDMOS gate and drain structure in the substrate
10
for an n-channel transistor.
As shown schematically in
FIG. 5
, the wire bonds connected to the gate input and to the drain output have associated input inductance
28
and output inductance
30
which combine with parasitic input capacitance
32
and output capacitance
34
to modify input and output impedances.
FIG. 6
is a plan view illustrating an input transmission line
40
, input wire leads
42
from transmission line
40
to bonding pads
20
of cells
12
, and wire leads
44
from bonding pads
18
to output transmission line
46
.
For wireless phone applications, signals with short wavelengths (up to the GHz range) must be amplified. Heretofore, the multicell LDMOS transistor has performed satisfactorily for frequencies up to 1 GHz. See
FIG. 7
which illustrates gate width versus CW power capability. For the 1 GHz curve
50
, a linear relationship exists between gate width and power. However, 2 GHz curve
52
shows a nonlinear effect where the cascading of additional cells produces a lesser increase in power.
The present invention is directed to providing a power transistor amplifier with improved power and performance capability.
SUMMARY OF THE INVENTION
We have discovered that the loss of performance, when cascading transistor unit elements in the frequency ranges where electrical length is on the same order as the physical length, stems from phase mismatch across the transverse direction of the die whereby destructive interference occurs between the unit elements and thus reduces performance.
In accordance with the invention, phase mismatch between cells or unit elements in a cascaded transistor is reduced to improve performance of the cascaded transistor. In one embodiment of the invention, inner unit elements of the cascaded array of elements have fewer transistor elements connected to bonding pads than do outer transistor elements. This physical shaping of the transistor cells in a bow tie configuration reduces the total gate width of the inner elements but produces improved performance by reducing phase mismatch between the inner elements and the outer elements. Additionally, input and output capacitance for each cell can be varied which alters input and output impedances of each cell, i.e. presenting a different impedance in some cells helps to phase match the signals across the transistor die.
In accordance with another embodiment of the invention, skin effects of input and output transmission lines which can cause an unbalance of current and voltage in a transmission line are overcome by use of wire bonds to the input and output transmission lines that are preferably concentrated near outer edges of the transmission lines where transverse electrical lengths are on the order of the physical lengths. Thus, each cell in the cascaded array can receive in-phase currents and in-phase voltages.
The invention and objects and features thereof will be more readily apparent from the following detailed description and dependent claims when taken with the drawings.
REFERENCES:
patent: 4408219 (1983-10-01), Resneau
patent: 5233310 (1993-08-01), Inoue
patent: 5949106 (1999-09-01), Kai et al.
patent: 6023080 (2000-02-01), Kojima
patent: 63240077 (1988-05-01), None
Miscellaneous Abstract re Phase Effect on Parallel Transistors, Oct. 8, 1999, pp. 1-11. Henry K. Woodward.
Bartlow Howard D.
Knorr Christopher J.
Parker James R.
Sevic John F.
Shingleton Michael B
Townsend and Townsend / and Crew LLP
UltraRF, Inc.
Woodward Henry K.
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