Amplifiers – With semiconductor amplifying device – Including plural amplifier channels
Reexamination Certificate
2001-12-18
2003-09-16
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural amplifier channels
C330S307000, C330S286000
Reexamination Certificate
active
06621347
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to high-output RF power amplifiers and, more particularly, to a push-pull RF power amplifier.
An RF power amplifier for data transmission used in radio communication equipment represented by a mobile phone has been required to be smaller in size and perform a high-output and high-efficiency operation. As an example of means for increasing the output of the power amplifier, there has been known a push-pull power amplifier circuit which operates power amplifying elements composed of a pair of field-effect transistors (TFTs) in phase opposition, combines output signals from the individual FETs, and outputs a resultant signal.
CONVENTIONAL EMBODIMENT 1
A description will be given herein below to an RF power amplifier according to a first conventional embodiment disclosed in Japanese Unexamined Patent Publication No. HEI 11-251849 with reference to the drawings.
FIG. 4
shows a circuit structure of the push-pull RF power amplifier according to the first conventional embodiment disclosed in the foregoing publication.
As shown in
FIG. 4
, the RF power amplifier comprises: a power distributing circuit
102
for distributing a signal inputted to an input terminal
101
such that first and second distributed signals having the same amplitude and a phase difference of 180° therebetween are outputted therefrom; an amplifier main body portion
103
composed of a pair of FET elements
103
a
which have a common source and respective gates for receiving the first and second distributed signals, perform power amplification with respect to the first and second distributed signals, and output first and second amplified signals; and a power combining circuit
105
which receives the first and second amplified signals, combines the first and second amplified signals that have been received, and outputs a resultant signal to an output terminal
104
.
Between the power distributing circuit
102
and the amplifier main body portion
103
, there is provided an input matching circuit
107
for matching the impedance of an input-side device connected to the input terminal
101
and the input impedance of the amplifier main body portion
103
via a pair of input capacitors
106
for interrupting a dc signal which are provided on the input side.
Between the amplifier main body portion
103
and the power combining circuit
105
, there is provided an output matching circuit
109
for matching the output impedance of the amplifier main body portion
103
and the impedance of an output-side device connected to the output terminal
104
via a pair of output capacitors
108
for interrupting a dc signal which are provided on the output side.
The input matching circuit
107
is composed of: a pair of microstrip lines
107
a
connecting each of the input capacitors
106
to the amplifier main body portion
103
in series; and an input matching capacitor
107
b
for connecting the pair of microstrip lines
107
a
to each other. Likewise, the output matching circuit
109
is composed of: a pair of microstrip lines
109
a
for connecting the amplifier main body portion
103
to each of the output capacitors
108
in series; and an output matching capacitor
109
b
for connecting the pair of microstrip lines
109
a
to each other.
Gate bias terminals
110
to each of which a gate bias signal is applied are connected to the respective gates of the FET elements
103
a
of the amplifier main body portion
103
via respective lines
111
. The gate bias terminals
110
are grounded via respective capacitors
112
.
Likewise, drain bias terminals
113
to each of which a drain bias signal is applied are connected to the respective drains of the FET elements
103
a
of the amplifier main body portion
103
via respective lines
114
. The drain bias terminals
113
are grounded via respective capacitors
115
.
CONVENTIONAL EMBODIMENT 2
A description will be given next to a push-pull RW power amplifier according to a second conventional embodiment with reference to the drawings.
FIG. 5
shows the amplifier main body portion
103
formed on a package
201
prior to sealing. The second conventional embodiment is different from the first conventional embodiment in that the amplifier main body portion
103
is provided with a first tertiary harmonic control circuit
211
and a second tertiary harmonic control circuit
212
.
As shown in
FIG. 5
, the package
201
is provided with: the pair of FET elements
103
a;
a pair of input terminals
202
for receiving the first and second distributed signals from the power distributing circuit
107
shown in
FIG. 4
; and a pair of output terminals
203
for outputting the first and second amplified signals. Between the input terminals
202
and the FET elements
103
a,
there are provided a pair of input terminal electrodes
205
and a pair of internal input matching transmission lines
206
which are electrically connected to each other via bonding wires
204
. Likewise, a pair of internal output matching transmission lines
207
and a pair of output terminal electrodes
208
which are electrically connected to each other via bonding wires
204
are provided between the FET elements
103
a
and the output terminals
203
.
A first high dielectric substrate
209
is provided under each of the internal input matching transmission lines
206
, while a second high dielectric substrate
210
is provided under each of the internal output matching transmission lines
207
.
Each of the internal input matching transmission lines
206
on the first high dielectric substrate
209
is connected to the first tertiary harmonic control circuit
211
. The first tertiary harmonic control circuit
211
is constituted by: a pair of microstrip lines
211
a
having respective one ends connected individually to the internal input matching transmission lines
206
; and a chip capacitor
211
b
interposed between and connected to the respective other ends of the pair of microstrip lines
211
a.
Each of the microstrip lines
211
a
has a length corresponding to {fraction (1/12)} of the fundamental wavelength &lgr; of an input signal.
Likewise, each of the internal output matching transmission lines
207
on the second high dielectric substrate
210
is connected to the second tertiary harmonic control circuit
212
. The second tertiary harmonic control circuit
212
is constituted by: a pair of microstrip lines
212
a
having respective one ends connected individually to the internal output matching transmission lines
207
and a chip capacitor
212
b
interposed between and connected to the respective other ends of the pair of microstrip lines
212
a.
Each of the microstrip lines
212
a
also has a length corresponding to {fraction (1/12)} of the fundamental wavelength &lgr; of an input signal.
A description will be given herein below to the characteristics of the RF power amplifier circuit according to the second conventional embodiment.
To obtain a high output from each of the FET elements, it is normally required to increase the gate width of the FET element. The increased gate width reduces each of the input/output impedances of the FET element so that the impedance ratio between the FET element and an external matching circuit is increased. As a result, a loss in converting the impedance of the matching circuit is increased disadvantageously.
To prevent the increased loss, the RF amplifier according to the conventional embodiment has the first and second high dielectric substrates
209
and
210
provided in proximity to the input/output terminals
202
and
203
of each of the FET elements
103
a,
respectively, thereby accomplishing conversion such that the impedance is maximized in the vicinity of the FET element
103
a
and suppressing a loss in impedance conversion resulting from the matching circuit provided externally. Such a circuit is termed an internal matching circuit because it is provided within the package
201
.
As is well known, the first and second distributed signals inputted to each of the FET elements
103
a
are amplified a
Ishida Hidetoshi
Katsuno Motonari
Maeda Masahiro
Morimoto Shigeru
Cole Thomas W.
Mottola Steven J.
Nixon & Peabody LLP
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