RF amplifier with reduced power consumption

Telecommunications – Transmitter and receiver at same station – Radiotelephone equipment detail

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Details

330296, H04B 138, H03F 304

Patent

active

061225320

ABSTRACT:
Accordingly, an RF amplifier with reduced power consumption is disclosed. In one embodiment, the RF amplifier includes first and second transistors for amplifying signals. The first transistor has a gate coupled to an input signal source. The second transistor has a gate coupled to the gate of the first transistor for signals in the operating frequency range of the amplifier. The second transistor also has a drain terminal coupled to the drain of the first transistor for signals in the operating frequency range. A first bias voltage generator circuit coupled to the gate of the first transistor provides a first bias voltage to the gate of the first transistor. Likewise, a second bias voltage generator circuit coupled to the gate of the second transistor provides a second bias voltage to the gate of the second transistor. An impedance connected between the source of the second transistor and the drain of the first transistor conducts a bias current. The first and second transistors each conduct a varying current in response to an input signal from the input signal source. In one embodiment, a load impedance coupled to the drain of the second transistor conducts a variable current generated by the first and second transistors and converts the variable current into an output voltage. The amplifier consumes only half the power of a single-transistor amplifier with the same effective device width and distortion level.

REFERENCES:
patent: 5392004 (1995-02-01), Masliah
patent: 5493255 (1996-02-01), Murtojarvi
patent: 5548248 (1996-08-01), Wang
patent: 5764107 (1998-06-01), Stone
patent: 5889433 (1999-03-01), Honma
patent: 5923215 (1999-07-01), Hans
patent: 5929710 (1999-07-01), Bien
AACD '98, Workshop on Advances In Analog Circuit Design, Hotel Richmond, Copenhagen, Denmark, "Design of Broadband Low-Noise Amplifiers in Deep-Submicron CMOS Technologies," Johan Janssens and Michiel Steyaert, Apr. 28-30, 1998.

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