Amplifiers – Involving structure other than that of transformers per se – With printed circuits
Reexamination Certificate
2002-01-28
2003-09-09
Pascal, Robert (Department: 2817)
Amplifiers
Involving structure other than that of transformers per se
With printed circuits
C330S286000, C330S310000
Reexamination Certificate
active
06617919
ABSTRACT:
BACKGROUND OF THE INVENTION
CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 USC 1119 to Japanese Patent Application No. 2001-20507, filed on Jan. 29, 2001, the entire content of which are incorporated by reference herein.
The present invention relates to an RF amplifier and, more particularly, to an amplifier with a plurality of amplification stages.
As an RF amplifier for amplifying an RF signal of 1 GHz or more, an amplifier used as the transmission terminal of, e.g., a personal handy phone system (to be referred to as a PHS hereinafter) and related to the present invention will be described.
Such an RF amplifier often uses a source-grounded amplifier formed of a GaAs MESFET (Metal Semiconductor Field Effect Transistor). In this case, a gain of about 10 dB can be realized per amplification stage, and an RF MMIC (Monolithic Microwave Integrated Circuit) formed of two to four amplification stages is widely used.
Generally, such an MMIC is encapsulated in a plastic package which is an inexpensive package. To realize an MMIC as compact as possible, a package with a minimum number of leads is employed.
FIG. 1
shows, as an example of the RF amplifier related to the present invention, an arrangement in which an amplification circuit MMIC with two amplification stages is packaged in a plastic package PKG with six pins LIN, LOUT, LVd
1
, LGND
1
, LGND
2
_
1
, and LGND
2
_
2
.
The amplification circuit MMIC is mounted on a bed BD, and respective pads PIN, POUT, PVd
1
, PGND
1
, and PGND
2
of the amplification circuit MMIC and the corresponding terminals LIN, LOUT, LVd
1
, LGND
1
, and LGND
2
_
1
and LGND
2
_
2
are connected to each other through bonding with wires W.
FIG. 2
shows a state wherein the amplification circuit MMIC encapsulated in the plastic package PKG is mounted on a printed wiring board PWB serving as a mother board. Patterned signal lines SIN and SOUT, power supply line SVd
1
, and ground surfaces SGND
1
and SGND
2
are formed on the printed wiring board PWB, and are connected to the corresponding terminals LIN, LOUT, LVd
1
, LGND
1
, and LGND
2
_
1
and LGND
2
_
2
with solder.
The lower surface of the printed wiring board PWB has a ground surface (not shown). The ground surfaces SGND
1
and SGND
2
formed on the upper surface of the printed wiring board PWB extend through via holes VH
1
, and via holes VH
1
and VH
2
, respectively, to be connected to the ground surface on the lower surface of the printed wiring board PWB.
FIG. 3
is an equivalent circuit diagram showing the configuration of the amplification circuit formed on the printed wiring board PWB.
GaAs MESFETs Q
1
and Q
2
form two source-grounded amplification stages. The drain of the MESFET Q
1
is connected to the power supply line SVd
1
, serving as a power supply system transmission line, through the pad PVd
1
and a parasitic inductance Lw_vd
1
parasitic on a lead and bonding wire. The gate of the MESFET Q
1
is connected to the signal line SIN through the pad PIN and a parasitic inductance Lw_in, and its source is grounded through the pad PGND
1
and a parasitic inductance Lw_gnd
1
.
The drain of the MESFET Q
2
is connected to the signal line SOUT, serving as an output system transmission line, through the pad POUT and an inductance Lw_out, its gate is connected to the drain of the MESFET Q
1
through a capacitor Cs, and its source is grounded through the pad PGND
2
and an inductance Lw_gnd
2
.
A ballast resistor Rst
1
is connected between the gate and source of the MESFET Q
1
, and a ballast resistor Rst
2
is connected between the gate and source of the MESFET Q
2
.
The inductance Lw_vd
1
, power supply line SVd
1
, and interstage capacitor Cs form an interstage matching circuit. The respective parasitic inductances are accounted for by the sum of the inductances of the bonding wires and leads connected to the pads of the amplification circuit MMIC, the ground surface on the printed wiring board PWB, and the via holes VH, as described above.
With this configuration, the ground surface formed on the lower surface of the printed wiring board PWB serves as a ground node for supplying a true ground potential. Accordingly, the ground pads PGND
1
and PGND
2
of the amplification circuit MMIC electrically float from their true ground surfaces through the parasitic inductances Lw_gnd
1
and Lw_gnd
2
.
Therefore, the ground surfaces, to which the ground pad PGND
1
of the MESFET Q
1
of the first amplification stage and the ground pad PGND
2
of the MESFET Q
2
of the second amplification stage are respectively connected on the printed wiring board PWB, are separated from each other. This is because if the first and second amplification stages of the amplification circuit MMIC share the same ground surface, a positive feedback path may be formed to extend from the source of the MESFET Q
2
of the second stage to the source of the MESFET Q
1
of the first stage, to undesirably cause the amplifier to oscillate.
On the other hand, if the parasitic inductance present between the true ground surface and the pads PGND
1
and PGND
2
is large, the gain of the amplifier decreases. To suppress such a decrease in gain, the numbers of wires and leads assigned to the node for supplying the ground potential in the amplification circuit MMIC may be increased. When the number of leads is increased, however, the package cost increases.
In this manner, with the amplifier described above, when a high gain is to be obtained, the number of leads increases and the package cost increases.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided an RF amplifier in which an amplification circuit with at least two amplification stages is mounted on a printed wiring board, comprising a ground node formed in the amplification circuit to commonly supply a ground potential to all the amplification stages, a first ground surface formed on the printed wiring board to supply a ground potential on an input system transmission line that transmits an input signal to be supplied to the amplification circuit, and a second ground surface, which is formed on the printed wiring board to supply a ground potential on an output system transmission line that transmits an output signal output from the amplification circuit, is electrically separated from the first ground surface on the printed wiring board, and is connected to the first ground surface through the ground node in the amplification circuit.
REFERENCES:
patent: 4465979 (1984-08-01), Russo
patent: 5990736 (1999-11-01), Nasuno et al.
patent: 6300827 (2001-10-01), King
patent: 6329879 (2001-12-01), Maruyama et al.
patent: 4-261205 (1992-09-01), None
patent: 10-173568 (1998-06-01), None
Kabushiki Kaisha Toshiba
Nguyen Khanh Van
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Pascal Robert
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