Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-07-12
2001-01-30
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185110
Reexamination Certificate
active
06181607
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor memories and in particular to arrays of flash memory cells designed to prevent program and erase disturb.
2. Description of Related Art
One of the problems associated with a flash memory is bit line and word line disturbs which are caused by bit line and word line voltages being coupled to the deselected cells as well as the selected cells on the same bit line or word line during erase, program and read operations. The effect of the bit line and word line disturb is to change the threshold voltage of the disturbed cells. This is an accumulative effect that over time will cause a memory error, will shorten the program and erase cycles, and reduce product life.
In U.S. Pat. No. 5,777,924 (Lee et al.) a flash memory circuit erases adjacent row simultaneously and eliminates over erasure and source disturbance problems associated with conventional flash memories. In U.S. Pat. No. 4,999,812 (Amin) an EEPROM device provides increased speed with lower susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming voltage or erase voltage to the path between the sense amplifiers and the memory array.
A split-gate cell is well known in industry today and has a structure equivalent to two transistors in series. One of the two transistors is an enhancement gate transistors and the other is a stacked gate transistor. These two transistors are geometrically joined with the gate of the enhancement transistor being the control gate of the stacked gate transistor. The stacked gate transistor performs like a conventional simple stacked gate cell, where its floating gate is formed by a first layer polysilicon under a control gate made from a second layer polysilicon. The number of electrons stored on the floating gate changes the threshold of the stacked gate transistor which determines the value of the stored data on the floating gate. The enhancement gate of the split gate cell performs as a selector for the stacked gate transistor, and has a positive threshold voltage (approximately 0.7 Volt). This allows the enhancement gate to act as a good selector for accessed cells and a good isolator for deselected cells without consideration of the threshold voltage of the stacked gate transistor.
Bit line and wordline disturb conditions occur in memory arrays that use split gate cells. This can occur during programming and reading when a combination of voltages must be applied to a particular split gate cell but also extend to other cells that are deselected. A disturb condition also occurs during erasure of a column of cells where word lines for the cells in the column are at a high negative potential and extend to other cells in other columns that are deselected and inhibited for erasure. Although a particular operation (read, program or erase) are not carried out in the other cells that are inhibited, the bias on a bit line or a word line extends to the other cells that are inhibited and can reduce the charge on the floating gates of those cells, albeit at a slow rate. The charge on the floating gate of a split gate cell determines the threshold voltage which determines the logical value of tie stored data on the stacked gate portion of the split gate cell. The charge can be reduced over time from repeated disturb operations until the threshold voltage of the stacked gate portion of the cell drops below a point where the stored value is in error.
SUMMARY OF THE INVENTION
In the present invention a reverse split gate cell is described along with its interconnection in a flash memory array that eliminates bit line and word line disturb conditions. In the conventional split gate cell the enhancement gate is associated with the source and the stacked gate is associated with the drain. In the reverse split gate cell the enhancement gate is associated with the drain and the stacked gate is associated with the source of the cell. As with the conventional cell, the drain of the reverse spit gate is connected to the bit lines of a flash memory array, but because the enhancement gate is associated with drain, the stacked gate is isolated from the bit lines when the drain is biased off.
In order to erase a reverse split gate cell a potential must be applied from the source to the enhancement gate. This will cause the cell to be erased by Fowler-Nordheim tunneling. In the designs used with the reverse split gate, source lines run in the direction of word lines. Since the stacked gate is associated with the source and the source is tied to a source line, a row of cells (or two rows of cells since it is common to double up on source lines to save layout space) will be erased at one time. A positive voltage is applied to the source line and a negative voltage is applied to the word lines connected to the enhancement gates of the cells to be erased. The bit lines connected to drains of the cells being erased are biased at zero volts or preferably left floating. This keeps the drain of the erased cells turned off, as well as drains in other rows not being erased, and isolates the bit lines from a possible disturb condition. The source line can be segmented to create more than one section along a source line which can be independently erased. This requires selectors in series with the source line to connect the source line erase voltage to only a portion of the source line. The word lines associated with the segmented rows of cells being erased extend to other cells in segments of the rows which are not being erased. These cells are not affected by the word line voltage since both their drain and source voltages are held at zero volts. One or more source lines can be activated by the application of a positive voltage connected to each source line by a segment control switch. This coupled with the ability to connect a negative voltage to one or more word lines allows the erasure of flash memory cells ranging from those connected to one segmented source line to the entire array.
To program a cell, a source line connected to the source of the cell to be programmed must have an applied voltage. The bit line connected to the drain of the cell to be programmed is connected to circuit ground, and the word line associated with the cell to be programmed is connected to a positive voltage greater in magnitude that the voltage connected to the source line. This causes a heavy current to flow in a backward direction in the channel from source to drain and induces a mechanism called “impact ionization” which creates an abundance of electron-hole pairs near the source of the cell. A large number of electrons are injected into the floating gate promoted by the electric field across the enhancement gate to source. Other word lines not being used for programming a cell are biased off as are other source lines not involved in programming the cell, preventing a disturb condition to occur. Bit lines connected to other cells in a row not being programmed are biased at the same voltage as the source line of the programmed cell. This prevents programming current from flowing in the cells not being programmed but connected to the word line of the cell being programmed. The positive voltage connected to the other bit lines also does not cause a problem in cell rows not biased by a word line or a source line because the enhancement gate is biased off, blocking the voltage on the bit lines. Thus programming a reverse spilt gate memory cell does not produce a disturb condition for other cells not being programmed.
The source line can run in parallel with the word lines for a portion of the source line length. Over this portion of the source line a metal layer can be connected to the source line in a plurality of contacts which is sometimes called metal-strapping. This metal strapping reduces the resistance of the source line and improves performance. A plurality of these metal-strapped source lines can be coupled together to achieve erasure of
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Le Vu A.
Saile George O.
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