Reversed phase-locked loop

Details Reversed phase-locked loop Reversed phase-locked loop

1994-06-10

1996-01-30

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 331 16, 331 17, 331DIG2, 327105, 327156, 327159, H03L 708, H03L 7085, H03L 718

Patent

active

054883326

ABSTRACT:
A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal. In addition, a selective grounding network is connected to the reference oscillator input of the PLL frequency synthesizer to greatly reduce power consumption of the PLL frequency synthesizer, and as part of the same effort, a voltage switch is utilized to remove power to the VCO.

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