Reverse electroplating of barrier metal layer to improve...

Details Reverse electroplating of barrier metal layer to improve... Reverse electroplating of barrier metal layer to improve...

2000-07-07

2001-07-17

Mills, Gregory (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Having liquid and vapor etching steps

C438S687000, C438S927000, C438S725000, C438S694000, C438S723000, C438S704000, C204S166000

Reexamination Certificate

active

06261963

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for filling contact openings and vias with copper and creating copper interconnections and lines.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to contacts to active areas, such as N
+
(P
+
) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Increased resistance and electromigration are undesirable for a number of reasons. For example, increased resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor. Additionally, electromigration effects in aluminum (Al) interconnects, where electrical currents actually carry Al atoms along with the electron “wind,” causing the Al atoms to electromigrate, may lead to degradation of the Al interconnects, formation of voids, further increased resistance, and even disconnection and/or delamination of the Al interconnects.
The ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration. Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes primarily because Al is inexpensive and easier to etch than, for example, copper (Cu). However, because Al has insufficient electromigration characteristics and high susceptibility to stress migration, it is typical to alloy Al with other metals.
As discussed above, as semiconductor device geometries shrink and clock speeds increase, it becomes increasingly desirable to reduce the resistance of the circuit metallization. The one criterion that is most seriously compromised by the use of Al for interconnects is that of conductivity. This is because the three metals with lower resistivities (Al has a resistivity of 2.824×10
−6
ohms-cm at 20° C.), namely, silver (Ag) with a resistivity of 1.59×10
−6
ohms-cm (at 20° C.), copper (Cu) with a resistivity of 1.73×10
−6
ohms-cm (at 20° C.), and gold (Au) with a resistivity of 2.44×10 ohms-cm (at 20° C.), fall short in other significant criteria. Silver, for example, is relatively expensive and corrodes easily, and gold is very costly and difficult to etch. Copper, with a resistivity nearly on par with silver, substantial immunity from electromigration, high ductility (which provides high immunity to mechanical stresses generated by differential expansion rates of dissimilar materials in a semiconductor chip) and high melting point (1083° C. for Cu vs. 659° C. for Al), fills most criteria admirably. However, Cu is difficult to etch in a semiconductor environment. As a result of the difficulty in etching Cu, an alternative approach to forming vias and metal lines must be used. The damascene approach, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25&mgr;) design rule conductive material-metallized circuits.
However, even with Cu interconnects, while electromigration effects are much less severe than with Al interconnects, some adverse electromigration effects remain and affect the performance of the Cu interconnects. In particular, electromigration voids may occur in Cu interconnects in vias, which are typically narrower than trenches and contact holes, due to the interaction of the electron wind and the Cu atoms. One or more barrier metal layers are typically used to protect silicon (Si) in the semiconductor devices from being poisoned by Cu atoms diffusing from the Cu interconnect into the Si. The barrier layer(s) at the bottom of openings such as contact holes, trenches, via, and the like, also contribute to the formation of electromigration voids by acting as a barrier between the Cu interconnect and the underlying Cu structure and/or line to which the Cu interconnect is connecting. The barrier layer(s) at the bottom of openings cause local heating, increasing the formation of electromigration voids, and also prevent Cu atoms in the Cu interconnect in the via from diffusing into the underlying Cu structure and/or line to which the Cu interconnect is connecting, further increasing the formation of electromigration voids.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.


REFERENCES:
patent: 5494860 (1996-02-01), McDevitt et al.
patent: 5814557 (1998-09-01), Venkatraman et al.
patent: 5925933 (1999-07-01), Colgan et al.
patent: 6030895 (2000-02-01), Joshi et al.
patent: 6184121 (2001-02-01), Buchwalter et al.

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