Reverse blocking semiconductor device and a method for...

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Rendering selected devices operable or inoperable

Reexamination Certificate

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Details

C438S212000, C257S327000, C257S329000, C257S492000, C257SE29013, C257SE29016, C257SE29198

Reexamination Certificate

active

07638368

ABSTRACT:
A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.

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Office Action issued in corresponding German Patent Application No. 10 2004 017 723.6-33, dated Feb. 5, 2008, with English translation.

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