Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1999-09-17
2001-09-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S106000
Reexamination Certificate
active
06291270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of production of a semiconductor device, more particularly relates to a method of production of a semiconductor device of a package format made small in size and high in density.
2. Description of the Related Art
In the VSLI and other semiconductor devices of recent years, the size has been reduced by 70 percent in three years and higher integration and higher performance have been achieved. Along with this, the package format of semiconductor devices has been reduced in size and increased in density.
In the related art, as the package format of a semiconductor device, the DIP (Dual Inline Package) or PGA (Pin Grid Array) and other through hole mount devices (THD) for mounting by inserting lead wires into through holes provided in a printed circuit board and QFP (Quad Flat (L-Leaded) Package) or TCP (Tape Carrier Package) or other surface mount devices (SMD) for mounting by soldering lead wires to the surface of a board have been used. Further, the industry is shifting to package formats such as BGA (Ball Grid Array) packages forming output terminals in grid array state.
On the other hand, there have been rising demands for greater reduction of size and increase of density of semiconductor devices. These can no longer be met with the above QFP and other package formats. For this reason, attention has focused on the package format referred to as “chip size packages” (CSP, also referred to as “FBGA (Fine-Pitch BGA)”) for realizing a further reduction of size and increase of density bringing the package size close to the size of the semiconductor chip as much as possible. Active study is now under way, and many proposals have been made.
An explanation will be made next of a semiconductor device of the above CSP format and a method for mounting it. For example, as shown in the sectional view of
FIG. 1A
, not illustrated electrode pads and a base board (interposer)
11
of a semiconductor chip
10
a
are mechanically and electrically connected by solder or other bumps
12
. Further, the space between the semiconductor chip
10
a
and the base board
11
is filled and sealed by a sealing resin
13
for protecting the connections by the bumps
12
. Further, the surface of the base board
11
opposite to the surface connected to the semiconductor chip
10
a
is formed with solder or other bumps
14
for connection to a mother board. The bumps
14
are connected to the bumps
12
connecting the electrode pads of the semiconductor chip
10
a
and the base board
11
via not shown through holes or other interconnections formed in the base board
11
. Due to these, a semiconductor device
100
of a CSP format is formed.
A mother board
2
for mounting the above semiconductor device
100
has lands (electrodes)
21
formed at positions corresponding to the positions of formation of the bumps
14
of the semiconductor device
100
to be mounted on the top surface of a board
20
made of, for example, a glass epoxy-based material and a not shown printed circuit formed on a front surface, on a back surface or on both surfaces of the board
20
connected to the lands
21
. The semiconductor device
100
is mounted on the mother board
2
by facing the bump forming surface of the semiconductor device
100
to the land forming surface of the mother board
2
while aligning the corresponding lands
21
and bumps
14
, and, as shown in
FIG. 1B
, by using a method of making the bumps
14
reflow etc., the semiconductor device
100
and the lands
21
of the mother board
2
are connected mechanically and electrically via the bumps
14
.
The above semiconductor device
100
has the base board (interposer)
11
acting as a buffer between the semiconductor chip
10
a
and the mother board
2
, but research and development for a CSP of a format applying packaging at a wafer level without using the above base board (interposer) are now being actively carried out for a further reduction of size, lowering of cost, and improvement of processing speed of electronic circuits.
An explanation will be made next of a semiconductor device of a CSP format not using the above base board (interposer) and the method for mounting it. For example, as shown in the sectional view of
FIG. 2A
, solder or other bumps
12
are formed connected to not illustrated electrode pads of the semiconductor device
10
a
. The surface of the semiconductor chip
10
a
in the space between the bumps
12
is sealed by a resin coating
15
. By this, a semiconductor device
1
of a CSP format is formed. On the other hand, the mother board
2
for mounting the semiconductor device
1
has the lands (electrodes)
21
and a not illustrated printed circuit on the top surface of board
20
made of for example a glass epoxy-based material in the same way as the above description. The above semiconductor device
1
is mounted on the mother board
2
by facing the bump forming surface of the semiconductor device
1
to the land forming surface of the mother board
2
while aligning the corresponding lands
21
and bumps
12
, and, as shown in
FIG. 2B
, by using a method of making the bumps
12
reflow etc., the semiconductor device
1
and the lands
21
of the mother board
2
are connected mechanically and electrically via the bumps
12
.
An explanation will be made next of the method of production of the above semiconductor device
1
of the CSP format by referring to the drawings. First, as shown in
FIG. 3A
, solder or other bumps
12
a
are formed on the semiconductor wafer
10
on which the circuit pattern of the semiconductor chip is formed so as to be connected to the circuit pattern of the semiconductor chip.
Next, as shown in
FIG. 3B
, the entire semiconductor wafer
10
is dipped in a molten resin to form a resin coating
15
on the bump forming surface of the semiconductor wafer
10
at a thickness that completely buries the bumps
12
a
while sealing the spaces between the bumps
12
a
. Here, with the method of dipping in a molten resin (dipping method), the resin coating
15
is formed on both surfaces of the semiconductor wafer
10
.
Next, as shown in
FIG. 4A
, the resin coating
15
is ground from the top of the bump forming surface of the semiconductor wafer
10
to reduce its thickness until parts of the bumps
12
a
are exposed.
Next, as shown in
FIG. 4B
, solder balls
12
b
are transferred connected to the bumps
12
a
. The bumps
12
are constituted by the bumps
12
a
and the solder balls
12
b.
Next, as shown in
FIG. 4C
, the semiconductor wafer
10
is cut (dicing step) along cutting lines comprised of regions between the circuit patterns of the semiconductor chips formed on the semiconductor wafer
10
and giving cutting margins of the semiconductor wafer
10
so as to divide it into semiconductor devices
1
of the CSP format each having cut semiconductor chips
10
a
and unnecessary parts
3
comprised of the outer periphery of the semiconductor wafer
10
not having complete circuit patterns.
The semiconductor device
1
produced by the above method of production can be mounted on the mother board as it is after dicing the semiconductor wafer
10
, and enables a reduction of costs and a shortening of a delivery compared with conventional semiconductor devices using a base board (interposer).
In the above method of production of a semiconductor device, however, it is difficult to cut the semiconductor wafer accurately in position along the cutting lines serving as the cutting margin on the semiconductor wafer. This is because if a resin coating is formed with respect to a semiconductor wafer
10
which has circuit patterns as shown in for example FIG.
5
A and the bumps
12
connected to the patterns and in which the regions between adjoining circuit patterns become the cutting lines
16
, as shown in
FIG. 5B
, the cutting lines
16
formed by the regions between adjoining circuit patterns will end up being covered over the entire region on the semiconductor wafer
10
, therefore even if trying to cut the semicondu
Le Dung A
Nelms David
Sonnenschein Nath & Rosenthal
Sony Corporation
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