Reusable modules for complex integrated circuit devices

Details Reusable modules for complex integrated circuit devices Reusable modules for complex integrated circuit devices

1998-07-22

2001-02-27

Grant, William (Department: 2121)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S098000, C700S121000, C710S009000, C710S022000, C710S105000, C710S119000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06195593

ABSTRACT:

TECHNICAL FIELD
The present invention generally pertains to integrated circuits and integrated circuit design processes. The present invention pertains more particularly to integrated circuit design processes and integrated circuits that employ reusable modules to reduce time and costs required for design and implementation.
BACKGROUND ART
Integrated circuit design processes have evolved quickly to keep pace with the rapid growth in integrated circuit (IC) complexity. Early IC devices, known as Small Scale Integration chips, had relatively few logic gates. Later, as IC technology advanced, it became possible to implement Medium Scale Integration chips with hundreds of logic gates. With the arrival of Large Scale Integration, thousands of logic gates could be implemented on a single chip.
As IC complexity increased, IC design became more complicated and increasing interest was shown in automated processes that could assist chip designers with design and implementation activities. Electronic Design Automation (EDA) tools were developed and these tools have continued to evolve with the arrival of Very Large Scale Integration (VLSI), which initially allowed single chips to carry hundreds of thousands of transistors.
Present EDA tools permit a chip designer to specify a chip in abstract, functional terms using a Hardware Description Language (HDL), translate the HDL design description into a gate-level description, layout the placement of gates and route connecting paths, and generate a mask for chip fabrication. Two examples of HDL include Verilogo® HDL, developed by Gateway Design Automation, and VHSIC HDL (VHDL), developed under contract from the U.S. Dept. of Defense.
Throughout the remainder of this disclosure, VHDL and especially Verilog HDL are discussed but no other description language is mentioned. It should be understood that many of the concepts discussed herein, particularly those of the present invention, are not limited to these two languages but instead are applicable to a wide range of languages.
Verilog HDL allows a designer to specify a chip in terms of modules that are described at any or all of four levels of abstraction: functional or algorithmic (behavioral-level), flow of data (dataflow-level), gates and interconnections (gate-level), or switches, storage nodes and connections between them (switch-level). The behavioral level is the most abstract level and is independent of device implementation details. The switch level is the least abstract and is very dependent on device implementation details. Modules are generally hierarchical, meaning that higher-level, more complex modules incorporate one or more lower-level, less complex modules. At some level, a module usually represents some component such as a storage register, a multiplexor or a UART (Universal Asynchronous Receiver/Transmitter).
A number of EDA tools for Verilog HDL and VHDL have automated a number of design steps including functional simulation and logic synthesis. Manual intervention is required, however, to manage the overall process, verify functional design, and ensure design requirements are achieved. Considerable manual effort is required to design chips that must meet stringent requirements such as high speed operation, small die size, wide temperature ranges, or low power requirements. Chips for microprocessors and random access memory (RAM) usually must be designed manually to achieve optimal performance because the automated tools are not yet good enough. This is particularly true for submicron technologies because layout decisions can dominate timing characteristics.
Further advances in VLSI technology permit fabrication of chips with millions of transistors. Circuits of such complexity can implement complete systems that formerly were implemented on a main board and one or more ancillary boards. So called System-on-a-chip (SOC) devices and other complex devices often integrate proprietary modules from different vendors that do not adhere to any particular interface standard; therefore, “oglue logic” or interface circuitry must be designed manually to interconnect these proprietary modules. The time and effort required to design and implement this glue logic increases the time and the cost required to design and implement a chip.
DISCLOSURE OF INVENTION
It is an object of the present invention to eliminate or at least reduce the manual effort required to design special interface circuitry interconnecting modules in an integrated circuit. This object is achieved by practicing the techniques of the present invention that allow a hardware designer to reuse pre-designed modules without the need to implement special-purpose glue logic.
According to the techniques of one aspect of the present invention, an integrated circuit device comprises a plurality of electrical connections accessible outside the device; a bus comprising a plurality of conductive paths internal to the device; a first module having a first interface circuit connected to the bus that operates according to a bus-access protocol, a first data path circuit coupled to the first interface circuit, one or more first registers coupled to the first interface circuit, a first state machine coupled to one of the first registers and coupled to the first data path circuit so as to control the first data path circuit, and a first external interface circuit coupled to the first data path circuit and coupled to one or more of the electrical connections; and one or more second modules internal to the device, wherein each second module has a respective second interface circuit connected to the bus that operates according to the bus-access protocol, a respective second data path circuit coupled to the respective second interface circuit, one or more respective second registers coupled to the respective second interface circuit, and a respective second state machine coupled to one of the respective second registers and coupled to the respective second data path circuit so as to control the respective second data path circuit.
According to the techniques of another aspect of the present invention, a method for designing an integrated circuit device that includes a bus internal to the device comprises the steps of generating a first description of the device using hardware description language, the first description describing one or more modules each having a bus interface internal to the electronic device that couples to the bus and conforms to a bus access protocol; obtaining a third description of the device by combining the first description with one or more second descriptions, each of the second descriptions describing one or more modules each having a bus interface internal to the device that couples to the bus and conforms to the bus access protocol; specifying-design constraints and choice of implementation technology for the device; and generating the technology-dependent design specification by synthesizing the third description according to the design constraints and the choice of implementation technology.
According to the techniques of yet another aspect of the present invention, a medium readable by a machine conveys a program of instructions for interpretation by the machine to generate a technology-dependent design specification for an electronic device. The program of instructions describes the electronic device as comprising a bus comprising a plurality of conductive paths internal to the device; a first module that has a first bus interface circuit coupled to the bus that operates according to a bus-access protocol, a first data path circuit coupled to the first bus interface circuit, one or more first registers coupled to the first bus interface circuit, a first state machine coupled to one of the first registers and coupled to the first data path circuit so as to control the first data path circuit, and a first external interface circuit coupled to the first data path circuit and coupled to one or more of electrical connections external to the device; and one or more second modules each having a respective second bus

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