Return-to-hold switching scheme for DAC output stage

Details Return-to-hold switching scheme for DAC output stage Return-to-hold switching scheme for DAC output stage

2007-12-11

2007-12-11

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S118000

Reexamination Certificate

active

11476476

ABSTRACT:
A novel clock control circuit completely removes the inter-symbol interference (ISI) in the DAC output waveform without any significant increase in power consumption and silicon area of the DAC. The novel circuit does not increase the requirement for slew rate and bandwidth of the amplifier.

REFERENCES:
patent: 6061010 (2000-05-01), Adams et al.
patent: 6545622 (2003-04-01), Kamal et al.
patent: 6917316 (2005-07-01), Blackburn
“A Low Power Current Steering Digital to Analog Converter In 0.18 Micron CMOS”; Mercer et al.; Analog Devices Inc., Wilmington, MA USA; pp. 72-77, Aug. 2005.
“A 114-dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling”; Adams et al.; IEEE Journal of Solid-State Circuits; vol. 33, No. 12, Dec. 1998; pp. 1871-1878.

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