Retro-etch process for integrated circuits

Details Retro-etch process for integrated circuits Retro-etch process for integrated circuits

1980-07-21

1982-03-09

Massie, Jerome W.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29579, 29580, 156653, 156657, 1566611, 156662, H01L 2122, H01L 21308

Patent

active

043187595

ABSTRACT:
A method of electrically isolating a plurality of semiconductor integrated circuit components and for forming gate elements for silicon gate transistors is disclosed whereby extremely narrow line widths can be formed which heretofore have been unattainable by practicing conventional photolithography.

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patent: 3595713 (1971-07-01), Brebisson et al.
patent: 3861024 (1975-01-01), Napoli et al.
patent: 4040168 (1977-08-01), Huang
patent: 4042726 (1977-08-01), Kaji et al.
patent: 4063992 (1977-12-01), Hosack
patent: 4124933 (1978-11-01), Nicholas
patent: 4239559 (1980-12-01), Ito
Benjamin, "Self-Aligned . . . Formation", IBM Technical Disclosure Bulletin, vol. 22, No. 7, (12/79) pp. 2749-2750.

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