Retro-etch process for forming gate electrodes of MOS integrated

Details Retro-etch process for forming gate electrodes of MOS integrated Retro-etch process for forming gate electrodes of MOS integrated

1981-03-05

1982-06-15

Massie, Jerome W.

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 148187, 156653, 156657, 156662, H01L 2122, H01L 2128

Patent

active

043343481

ABSTRACT:
A method of electrically isolating a plurality of semiconductor integrated circuit components and for forming gate elements for silicon gate transistors is disclosed whereby extremely narrow line widths can be formed which heretofore have been unattainable by practicing conventional photolithography.

REFERENCES:
patent: 3689332 (1972-09-01), Dietrich et al.
patent: 3920861 (1975-11-01), Dean
patent: 3951708 (1976-04-01), Dean
patent: 4037308 (1977-07-01), Smith
patent: 4060427 (1977-11-01), Barile et al.
patent: 4063992 (1977-12-01), Hosack
patent: 4176003 (1979-11-01), Brower et al.
patent: 4298402 (1981-11-01), Hingarh
Dienes et al., "Process . . . Geometrics", IBM Technical Disclosure Bulletin, vol. 21, No. 9 (2/79), pp. 3628-3629.

Affiliated with

Also associated with

Rating

Retro-etch process for forming gate electrodes of MOS integrated does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Retro-etch process for forming gate electrodes of MOS integrated, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Retro-etch process for forming gate electrodes of MOS integrated will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1913914