Retiming gated-clocks and precharged circuit structures

Details Retiming gated-clocks and precharged circuit structures Retiming gated-clocks and precharged circuit structures

1995-09-07

1997-07-01

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, G06F 1710

Patent

active

056444990

ABSTRACT:
A general set of timing constraints, along with methods for computing the "critical" elements of the set, i.e., the elements of the set that, if satisfied, are sufficient to guarantee proper circuit timing, enables retiming of VLSI systems incorporating gated clock signals and/or precharged circuit structures without changing the input/output behavior of the system. In one method, either the clock signal used by a system component is changed or alternatively, a new clock signal is generated for use in the system. In another method, a system component is retimed by retiming other system components. In a further method, multiple critical paths for each pair of components comprising the system are computed. The most critical path for each pair of components is selected and if the most critical path for a pair of components is not properly timed, one component of the pair is retimed in order to properly time the pair of components. If the most critical path is properly timed, or is properly timed after retiming, the procedure is repeated for another pair of components until each pair of components is properly timed so that the VLSI system is, in turn, retimed.

REFERENCES:
Ishii, Leiserson, and Papaefthymiou, "Optimized Two-Phase, Level-Clocked Circuitry" pp. 245-265.
Lockyear and Ebeling, "Optimal Retiming of Level-Clocked Circuits Using Symmetric Clock Schedules", IEEE Trans. on CAD and ICs, vol. 13 No. 9, Sep. '94, 1097-1109.
Lockyear & Ebeling, "Practical Application of Retiming to the Design of High-Performance Systems", Proceedings of 1993 IEEE/ACM Int'l. Conf on CAD, 288-295.
Papefthymiou & Randall, "TIM: A timing package for Two-Phase, Level-Clocked Circuitry", Proceedings From 30th (1993) ACM/IEEE Design Automation Conf, 497-507.
Szymanski, "Computing Optimal Clock Schedules", Proceedings 29th (1992) ACM/IEEE Des. Auto. Conf. 399-404.
Ishii, "Retiming Gated-Clocks and Precharged Circuit Structures" Proc. 1993 ACM/IEEE Conf. on CAD, 300-307.

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