Retiming circuits for phase-locked loops

Details Retiming circuits for phase-locked loops Retiming circuits for phase-locked loops

2008-01-01

2008-01-01

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S090000, C327S099000, C327S159000

Reexamination Certificate

active

11788560

ABSTRACT:
Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A multiplexer in communication with the first and second sampling circuits selects one of the samples as a retimed version of the frequency-divided clock. The particular sample selected is preferably the sample less likely to produce an erroneous retimed version of the frequency-divided clock.

REFERENCES:
patent: 6542017 (2003-04-01), Manganaro
patent: 6597229 (2003-07-01), Koyata et al.
patent: 6597299 (2003-07-01), Bugeja
patent: 6861881 (2005-03-01), Neravetla et al.
patent: 6864722 (2005-03-01), Adkisson
patent: 7129789 (2006-10-01), Hsiao et al.

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