Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1998-03-16
2001-01-23
Vo, Don N. (Department: 2734)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S371000, C375S375000
Reexamination Certificate
active
06178212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a retiming circuit, for example, a retiming circuit provided in an optical receiving unit in an optical data transmission system.
For example, when a logic “1” or “0” of an optical data signal transmitted from an optical transmitting unit at one end of the optical data transmission system is discriminated at the optical receiving unit placed at the other end thereof, desirably the discrimination is carried out at the center portion of each pulse corresponding to the logic “1” and “0”. This is because, generally, there is a lot of noise in the vicinity of the rising edge of each pulse and in the vicinity of the falling edge of each pulse, and therefore it is most correct to judge the logic “1” or “0” at the center portion where there is the least noise. For this reason, the phase between the input data and clock is adjusted so that each optical data signal received at the optical receiving unit, that is, the center portion of each input data, and the timing for the discrimination substantially coincide. This is done by the retiming circuit.
2. Description of the Related Art
As will be explained in more detail later by using the drawings, if the retiming circuit of the related art is adopted, the following two problems arise.
First, there is the problem that, according to the retiming circuit of the related art, the optimum phase clock (CLK) is selected by just the rising changing point of the input data (Din), therefore when there is a fluctuation in the duty, explained later, it is no longer possible to sample the center portion of a pulse. This is because the true center portion of the pulse must be determined by taking not only the rising changing point of the input data (Din), but also its falling changing point into account.
Second, there is the problem that, according to the retiming circuit of the related art, it is difficult to sample the center portion of each pulse with an extremely high precision for all of various input data (Din) from a large number of subscriber side equipment. This is because, in the retiming circuit of the related art, it is necessary to select one optimum phase clock from among limited number of types of clocks.
SUMMARY OF THE INVENTION
Accordingly, in consideration with the above problems, an object of the present invention is to provide a retiming circuit and a method for performing retiming able to always discriminate the logic at the center portion of each pulse even if the duty of the pulses fluctuates and, at the same time, able to make the center portion of a pulse coincide with the clock without error to operate at a high speed.
To attain the above object, according to the present invention, there is provided a retiming circuit provided with a delay means for imparting a variable delay to input data or a clock; a reference clock generating means for generating a reference clock synchronized with the clock; a first phase difference detection means for detecting the phase difference between a rising edge of the reference clock and a rising edge of the input data; a second phase difference detection means for detecting the phase difference between a rising edge of the reference clock and a falling edge of the input data; and an intermediate phase setting means for calculating the intermediate phase of the input data based on the outputs of the first and second phase difference detection means, the amount of the delay being controlled based on the intermediate phase. By this, even if there is a fluctuation in the duty of the pulse, sampling by the clock is always carried out at the center portion of the input data and the logic “1” and “0” is correctly discriminated.
REFERENCES:
patent: 4734900 (1988-03-01), Davie
patent: 5132957 (1992-07-01), Mashimo
patent: 5438303 (1995-08-01), Murakami et al.
patent: 5640131 (1997-06-01), Kawasaki et al.
patent: 6028898 (2000-02-01), Sparks et al.
patent: 7193562 (1995-07-01), None
patent: 2274947 (1997-11-01), None
Fujitsu Limited
Helfgott & Karas, P C.
Vo Don N.
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