Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
2000-09-27
2003-05-27
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C430S396000
Reexamination Certificate
active
06569576
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuits, and more particularly to reticles (masks) used during the fabrication of integrated circuits.
BACKGROUND
Integrated circuits (IC) typically comprise electronic circuitry made of individual devices that are coupled together to perform a certain function. To fabricate an IC that performs a function, a circuit schematic must be designed and then translated into a physical representation known as a layout using computer aided design (CAD) tools. The resulting layout is a translation of the discrete circuit elements of the circuit schematic into shapes that are used to construct individual physical components of the circuit such as gate electrodes, field oxidation regions, diffusion regions, and metal interconnections.
CAD tools that generate a layout are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. These design rules are often determined by certain processing and design limitations defined by the particular IC fabrication process to be used, for example, defining the space tolerance between devices or interconnect lines that prevent undesirable interaction between devices or lines. Design rule limitations are frequently referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between lines that can be supported by an IC fabrication process. Consequently, the critical dimension determines the overall size and density of the IC.
The layout is optically transferred onto a semiconductor substrate using a series of lithographic reticles and an exposure tool. Photolithography is a well-known process for transferring geometric shapes present on each reticle onto the surface of a semiconductor substrate (e.g., a silicon wafer) using the exposure tool including an ultra-violet (UV) or other light source. In the field of IC lithographic processing, a photo sensitive polymer film called photo resist is normally applied to the wafer and then allowed to dry. The exposure tool is utilized to expose the wafer with the proper geometrical mask patterns by transmitting UV light or other radiation through the reticles. After exposure, the wafer is treated to develop the mask images transferred to the photo sensitive material. These masking images are then used to create the device features of the circuit.
FIG. 1
is a perspective view showing a simplified conventional reticle
100
that is being used during the optical transfer of an integrated circuit portion onto a semiconductor substrate
110
. Reticle
100
includes an opaque masking material (e.g., chrome) that is deposited on a transparent substrate
102
and etched to form a lithographic mask pattern
105
. During an integrated circuit fabrication process, UV light or radiation emitted from an exposure tool (not shown) is transmitted through reticle
100
, thereby forming an image
112
of mask pattern
105
on semiconductor substrate
110
. As indicated by the tapered dashed lines in
FIG. 1
, the lithographic process typically utilizes an optical reduction system such that image
112
is substantially smaller than (e.g., ⅕th) the size of lithographic mask pattern
105
. Note that the resolution values of mask pattern
105
are indicated as a width W of a mask pattern portion
106
, and a space S between mask pattern portion
106
and mask portion
107
. Width W and space S represent the smallest dimensions that can be repeatedly transferred onto semiconductor substrate
110
by the exposure tool, and produce structures meeting the critical dimensions defined by the IC fabrication process.
The reticle is protected on the side where the chrome pattern resides with a pellicle. The purpose of the pellicle is to prevent dust particles that may cause pattern defects from gathering on the reticle. Since the pellicle is transparent and the pellicle surface that collects dust particles is located outside of the focal plane of the reduction lens in the exposure tool, particles that accumulate on the pellicle will not form repeating defects on the semiconductor substrate
110
. The reticle is also in contact with a pod, which holds the reticle in place during mask pattern transfer process. It has been found that electrostatic charge can accumulate on the pod and pellicle causing damage to the chrome pattern on the reticle. A damaged chrome pattern will be duplicated on the silicon substrate.
An important limiting characteristic of the exposure tool is its resolution value. The resolution value for an exposure tool is defined as the minimum mask pattern feature that the exposure tool can repeatedly expose onto the wafer.
Space S continues to decrease as improved stepper designs have allowed the resolution values of fabrication processes to decrease. Because the electrical field strength generated by the electrostatic charges on the adjacent patterns is inversely proportional to the pattern spacing, as the space S has decreased to sub-micron values, the probability of damage from electrostatic discharge has increased.
FIG. 2
is a plan view showing a portion of reticle
100
in which some of the masking material has melted and formed a bridge
210
between mask pattern portions
106
and
107
, thereby generating flaws in the IC formed on semiconductor substrate
110
(see FIG.
1
). The combination of dissimilar charges stored in mask pattern portions
106
and
107
and the small space S separating these portions results in electrostatic discharge and melting of the masking material to form bridge
210
.
U.S. Pat. No. 5,989,754 describes how accidental contact of the pod with a PVC glove causes electrostatic charges to form on the surface of the pod. The electrostatic charges are in turn induced onto the insulating surface of the reticle substrate and the chrome. U.S. Pat. No. 5,999,397 describes how to calculate the electrostatic charge potential on the reticle surface when a charge appears on the pod. Because the chrome patterns on the reticle are small, the charge per unit area can reach a critical value that will result in an electrostatic discharge damage to the chrome pattern such as the creation of bridge
210
between mask pattern portions
106
and
107
on FIG.
2
. The prior art proposed forming a plurality of metal lines to connect all of the chrome patterns on the reticle substrate. The dimension of the metal lines is designed to be smaller than the minimum feature size that can be resolved by the reduction lens of the exposure tool so that the metal lines will not be duplicated on the silicon wafer substrate. The metal lines spread the induced charge across all of the chrome patterns on the reticle to reduce the charge per unit area on the chrome patterns below the critical value that results in electrostatic discharge damage to the chrome pattern. As a result, the induced charge will not concentrate on a few chrome islands and cause damage.
One potential problem with forming a plurality of metal lines to connect all of the chrome patterns arises in the mask inspection procedure. Typically, reticles are optically inspected using automated tools that compare the patterns on the reticle to the desired pattern established by the original design. This reticle inspection is carried out prior to using the reticle in the manufacturing process to avoid duplication of faulty patterns if the reticle was improperly manufactured. It is difficult during inspection to differentiate the intended pattern for the circuitry and the metal line patterns introduced to prevent electrostatic discharge, which may result in false detection of faults that do not exist.
Another problem with introducing a plurality of metal lines to connect the patterns and distribute electrostatic charge is that as technology advances, the packing of circuitry becomes more and more dense. A typical set of reticles used to manufacture a given IC can contain hundreds of millions of patterns. The cost associated with adding hu
Ho Jonathan Jung-Ching
Hsueh Shih-Cheng
Look Kevin T.
Behiel Arthur J.
Brown Scott R.
Huff Mark F.
Mohamedulla Saleha R.
Xilinx , Inc.
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