Reticle and method of fabricating semiconductor device

Details Reticle and method of fabricating semiconductor device Reticle and method of fabricating semiconductor device

2002-01-25

2003-11-11

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S800000, C438S462000, C257S797000, C257S798000, C250S491100, C250S492200, C250S492220, C250S397000, C250S398000

Reexamination Certificate

active

06645823

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device fabrication and more particularly, to a reticle that improves the alignment or stacking accuracy in the lithographic process for fabricating semiconductor devices, and a method of fabricating a semiconductor device that uses a reticle improving the alignment or stacking accuracy in the lithographic process.
2. Description of the Related Art
The lithography technique, which is used to transfer patterns of geometric shapes for on a mask to a thin resist layer, plays an important role in the process sequence of fabricating Ultra-Large Scale Integrated semiconductor devices (ULSIs). To conduct the lithographic process adequately, there is the need to form minute patterns of geometric shapes on a reticle (hereinafter, reticle patterns) as correct as possible and to align or stack the reticle patterns to the patterns of an underlying layer at as high accuracy as possible.
With the reduction step-and-repeat projection exposure system (which is simply called the “stepper”), which has been usually used for the optical lithographic process in the ULSI fabrication process sequence, the optical lenses have some aberration and therefore, an image of the reticle patterns transferred to a resist layer on the semiconductor wafer has image distortion and positional distortion. The amount of the image and positional distortions varies dependent on the size and pitch of the reticle patterns.
To meet the above-described need to form the reticle patterns as correct as possible and to align the reticle patterns to the underlying layer at as high accuracy as possible, an improved reticle was developed and disclosed in the Japanese Non-Examined Patent Publication No. 10-213895 published in August 1998. The improved reticle includes alignment marks, each of which is formed by the combination of geometric shapes having the same size and the same shape as the geometric shapes that form the circuit pattern in each chip site of the wafer. For example, if the reticle is designed for circular or square contact holes, the alignment mark is formed by the combination of circular or square shapes having the same size as the circular or square contact holes. The circular or square shapes are arranged regularly to define the contour of the alignment mark.
With the improved reticle disclosed in the Publication No. 10-213895, the circuit patterns formed in the chip area and the alignment mark pattern formed in the scribe line area have a specific geometric correlation and thus, the amount of the image and positional distortions generated in the chip area is substantially equal to the scribe line area. Accordingly, the alignment or stacking accuracy of the circuit patterns in the chip area is correctly recognizable by measuring the alignment or stacking accuracy of the alignment mark. This makes it possible to cope with further miniaturization of circuit patterns in the optical lithographic process.
Next, the alignment mark of the improved reticle disclosed in the Publication No. 10-213895 is explained in more detail below with reference to FIG.
1
.
As seen from
FIG. 1
, the alignment mark
500
of the prior-art reticle comprises four rectangular mark elements
501
A,
501
B,
503
A, and
503
B, which are arranged to form an imaginary rectangle in the scribe line area of the reticle. The two elements
501
A and
501
B, which extend along the X-axis, are parallel to and apart from each other by a specific distance. The two elements
503
A and
503
B, which extend along the Y-axis perpendicular to the X-axis, are parallel to and apart from each other by a specific distance.
The prior-art reticle with the mark
500
is applied to the upper one of the two adjoining layers. Another alignment mark
600
due to another reticle, which is additionally shown by broken lines in
FIG. 1
, is formed on the lower one of the two layers. This is to exhibit the positional relationship between these marks
500
and
600
.
Similar to the upper-layer mark
500
, the lower-layer mark
600
comprises four rectangular mark elements
605
A,
605
B,
607
A, and
607
B, which are arranged to form an imaginary rectangle smaller than that of the mark
500
in the scribe line area. The two elements
605
A and
605
B, which extend along the X-axis, are parallel and apart from each other by a specific distance. The two elements
607
A and
607
B, which extend along the Y-axis perpendicular to the X-axis, are parallel and apart From each other by a specific distance. As shown in
FIG. 1
, the mark
500
is located to surround entirely the mark
600
.
FIG. 2
shows the detailed structure of the part
509
of the mark element
503
B of the mark
500
shown in FIG.
1
. As shown in
FIG. 2
, the part
509
of the element
503
B includes a pattern
510
comprising seven linear sub-elements
511
,
512
,
513
,
514
,
515
,
516
, and
517
with the same size and the same shape. These sub-elements
511
to
517
are formed to extend parallel to the Y-axis and are arranged along the X-axis at equal pitches p. The pitch p is equal to the pitch of the linear sub-elements of the circuit pattern formed in the chip area of the reticle. A plurality of the patterns
510
are arranged at regular intervals along the Y-axis, thereby forming the element
503
B.
The mark element
503
A has the same structure as the element
503
B shown in FIG.
2
. The alignment mark elements
501
A and
501
B have the structure obtained by turning the element
503
B by 90° around the center of the imaginary rectangle of the mark
500
.
When the prior-art reticle having the alignment mark
500
is used in the optical lithographic process, the following pattern is formed on an optical resist layer over a semiconductor wafer. The pattern formed in the resist layer is termed the “resist pattern” in the following explanation.
FIG. 3
shows an example of the resist pattern
520
obtained from the pattern
510
of the element
503
B of the prior-art alignment mark
500
, which is formed by conducting the optical lithographic process using an ideal optical system of a so-called stepper without any aberration.
As shown in
FIG. 3
, the resist pattern
520
comprises seven linear sub-elements
521
,
522
,
523
,
524
,
525
,
526
, and
527
corresponding to the seven linear sub-elements
511
,
512
,
513
,
514
,
515
,
516
, and
517
of the pattern
510
of the element
503
B. Since it is supposed that the optical system of the stepper includes no aberration, as shown in
FIG. 3
, the centerlines CL
21
, CL
22
, CL
23
, CL
24
, CL
25
, CL
26
, and CL
27
of the sub-elements
521
to
527
are respectively located on their specific reference positions. In other words, the centerlines CL
21
to CL
27
of the sub-elements
521
to
527
have no positional shift with respect to their reference positions.
FIG. 4
shows an example of the resist pattern
530
obtained from the pattern
510
of the element
503
B of the prior-art alignment mark
500
, which is formed by conducting the optical lithographic process using an actual optical system of a so-called stepper with aberration.
As shown in
FIG. 4
, the resist pattern
530
comprises seven linear sub-elements
531
,
532
,
533
,
534
,
535
,
536
, and
537
corresponding to the seven linear sub-elements
511
,
512
,
513
,
514
,
515
,
516
, and
517
of the pattern
510
of the element
503
B.
Since the optical system of the stepper includes some aberration, as shown in
FIG. 4
, the sub-elements
531
to
537
have positional shifts with respect to their reference positions (i.e., the sub-elements
521
to
527
in FIG.
3
), respectively. Specifically, the centerlines CL
31
, CL
32
, CL
33
, CL
34
, CL
35
, CL
36
, and CL
37
of the sub-elements
531
to
537
are respectively deviated from the centerlines CL
21
, CL
22
, CL
23
, CL
24
, CL
25
, CL
26
, and CL
27
located respectively on their reference positions by specific shifts C, D, E, F, G, H, and I. The shifts C and I of the sub-elements
531
and
537
located

Affiliated with

Also associated with

Rating

Reticle and method of fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reticle and method of fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reticle and method of fabricating semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3116219