1976-09-27
1978-04-25
Claffy, Kathleen H.
179 15BS, H04J 306
Patent
active
040864375
ABSTRACT:
A synchronization circuit for a system in which digital coded data is received by an exchange from a transmitting station in time division multiplex form and is transmitted in time division multiplex form. In such a system, the incoming data is received at a clock rate dependent on the clock of the transmitting station and is stored in a memory at that rate. Read out from the memory is at the exchange rate. Since only one operation in the memory, either read or write, can occur at a time, control must be imposed to separate in time the reading and writing operations. To provide this separation, a time shift equal in duration to one time slot is introduced to delay the later-started of two operations.
REFERENCES:
patent: 3829843 (1974-08-01), Cichetti
patent: 3928727 (1975-12-01), Roche
patent: 3970796 (1976-07-01), Gyurki
Coudray Andre Lucien
Henrion Michel André Robert
Chaban Marvin M.
Claffy Kathleen H.
International Standard Electric Corporation
Popek Joseph A.
Raden James B.
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