Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2000-04-25
2001-09-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S022000, C257S028000, C257S368000
Reexamination Certificate
active
06291832
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to electronic devices and more specifically to a method and system of fabricating a resonant tunneling diode latch.
BACKGROUND OF THE INVENTION
Existing complementary metal oxide silicon (CMOS) semiconductor devices that are produced in mass quantities are referred to as “bulk” CMOS, because they include a semiconductive bulk substrate on which active or passive circuit elements are disposed. Recently, silicon oxide insulator (SOI) devices have been introduced which consume less power than do bulk CMOS devices, an important advantage in many applications such as battery-powered mobile telephones and battery-powered laptop computers. Also, SOI devices advantageously operate at higher speeds than do bulk CMOS devices.
SOI devices are characterized by a thin layer of insulative material (the so-called buried oxide layer, or “SOI”) that is sandwiched between a bulk substrate and the circuit elements of the device. Typically, no other layers of material are interposed between the SOI and the bulk substrate.
FIG. 1
is a sectional view of an SOI substrate
10
. As shown in
FIG. 1
, by forming an SOI layer
12
and a buried oxide layer
14
on a semiconductor substrate, an SOI substrate is formed.
Additionally, resonant tunneling diodes (RTDs) also have a wide variety of high speed applications for CMOS devices. RTDs are two terminal devices with conduction carriers through potential barriers to yield current-voltage curves with portions exhibiting negative differential resistance. Because tunneling occurs through a potential barrier having a very narrow width, the frequency response of a resonant tunneling device is not limited by the diffusion or transit time of charge carriers. Instead, the frequency response is limited by the circuit capacitance and impedance of the device. The circuit capacitance and device impedance both scale directly with the area of the circuits and devices on the integrated circuit substrate, permitting devices to be down-sized to about the width of the potential barrier.
RTDs, however, have not been particularly useful for integrated circuit applications, primarily because the RTD is a two-terminal device, and the current-voltage characteristic of the RTD is dictated rather rigidly by the properties of the semiconductor material used in constructing the RTD.
More recently it has become known to use molecular beam epitaxy to grow atomically thin layers of single crystal material on a semiconductor substrate to construct tunnel barriers permitting one to engineer a device having a desired current-voltage characteristic. In particular, one may easily select the width of the barrier to adjust the tunneling current, and one may construct an array of barriers in series to increase the “peak” and “valley” voltages of the current-voltage characteristic. This ability to engineer the physical structure of the tunneling barriers provides a high degree of design flexibility quite independent of the properties of the semiconductor material used for fabricating the RTD.
FIG. 2
is a flow chart illustrating the conventional process steps required to fabricate a resonant tunneling diode. First, a heavily doped n+ silicon layer is provided, via step
20
. Next, a thin layer of undoped silicon is deposited over the n+ silicon layer, via step
22
. This serves as the tunneling barrier and is typically grown using molecular beam epitaxy. A heavily doped p+ silicon layer is then provided via step
24
. Finally, metal contacts are formed on each of the n+ and p+ silicon layers, via step
26
.
For a further illustration of the conventional technology, please refer to FIG.
3
.
FIG. 3
shows a conventional RTD
30
. The conventional RTD
30
comprises a heavily doped p+ silicon layer
32
, a thin layer of undoped silicon
34
, a heavily doped n+ silicon layer
36
and metal contacts
38
. Accordingly, the thin layer of undoped silicon
34
serves as a tunneling barrier between the doped silicon layers
32
,
36
.
Although the conventional molecular beam epitaxy methodology adequately forms RTDs in silicon, the slow rate at which it operates ultimately prohibits its use in the manufacturing of electronic devices.
Accordingly, what is needed is a method and system for forming a resonant tunneling diode in an SOI structure that will result in an increased throughput and that is easy to implement. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method/system for forming a resonant tunneling diode latch is disclosed. The method/system comprises the steps of forming a gate on a silicon substrate, the silicon substrate having at least one SOI layer disposed therein, providing an oxide spacer over the gate, providing a first ion implant in a first region of the silicon substrate, and then providing an oxide layer. The method further comprises polishing the oxide layer back to the gate, removing the gate, and providing a second ion implant in a second region of the silicon substrate wherein the first and second regions have an undoped portion of silicon there between.
According to the present invention, the method/system for forming a resonant tunneling diode latch in an SOI substrate that is easily implemented and results in an increased throughput of resonant tunneling diode devices.
REFERENCES:
patent: 5606177 (1997-02-01), Wallace et al.
patent: 5629546 (1997-05-01), Wu et al.
patent: 5757051 (1998-05-01), Wu et al.
Advanced Micro Devices , Inc.
Le Dung A
Nelms David
Sawyer Law Group LLP
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