Resolver arrangement

Coded data generation or conversion – Phase or time of phase change – Synchro or resolver signal

Reexamination Certificate

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Details

C341S143000

Reexamination Certificate

active

11347703

ABSTRACT:
A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output. Each of the processing channels includes a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil. Each channel also includes a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words. In addition, each channel has a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words. Finally, each channel has a second digital filter that averages the demodulated data-words and supplies digital output data-words on the channel output, the carrier signal being suppressed in the output data-words.

REFERENCES:
patent: 3800228 (1974-03-01), Acker
patent: 6218972 (2001-04-01), Groshong
patent: 7127932 (2006-10-01), Morell et al.
patent: 2002/0173931 (2002-11-01), Dudler et al.
patent: 19841763 (1998-09-01), None
patent: 10306127 (2003-02-01), None
patent: 08149876 (1996-07-01), None

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