Resistor structure and process

Fishing – trapping – and vermin destroying

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437 48, 437 52, 437 60, 437918, H01L 2170

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052368572

ABSTRACT:
A method of forming an integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

REFERENCES:
patent: 4377819 (1983-03-01), Sakai et al.
patent: 4418468 (1983-12-01), Uora et al.
patent: 4653176 (1987-03-01), Van Ommen
patent: 4949153 (1990-08-01), Hirao et al.
patent: 5013678 (1991-05-01), Winnerl et al.
IEDM Disclosure Bulletin, vol. 23, No. 2, May 1981 pp. 5392-5394.

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